Patent US3673428A successfully refreshed from Google Patents.
US3673428A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Input transient protection for complementary insulated gate field effect transistor integrated circuit device
Assignee: RCA Corp
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Filing: 1970-09-18
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Granted: 1972-06-27
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Expires: 1990-09-18
Abstract
Abstract In a CMOS integrated circuit of the type which includes a diffused P type region in which the N type transistors are formed, a resistor-region is provided by diffusion at the same time as that P type region. A diode having low breakdown is established by forming P+ type regions or N+ type regions in electrical communication with the resistor so that the diode breakdown is effectively dominated by the impurity concentration characteristics of the P+ type or N+ type regions.
Inventors
- 👤 Terry George Athanas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 21:27
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/811; H10D84/82; H10D84/83; H10D84/85; H10D89/00; H10D89/60; H10D89/601; H10D89/611; Y; Y10; Y10S; Y10S148/00; Y10S148/049; Y10S148/145
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
255 words
In a semiconductor device of the type which has a body of semiconductive material of one type and degree of conductivity and which further has a plurality of diffused regions in said body adjacent to a surface thereof for defining active and passive circuit elements including a pair of insulated gate field effect transistors, one of which has spaced source and drain regions in said body adjacent to said surface and the other having a diffused well region of conductivity type opposite to that of said body in said body adjacent to said surface and a pair of source and drain regions of said one type conductivity within said well region, resistor and diode elements characterized by relatively high resistance and relatively low diode breakdown strength, respectively, comprising: a diffused resistor region, of said opposite type conductivity and having the same depth and impurity concentration gradient as said diffused well region, in said body adjacent to said surface and defining a gradual PN junction in said body, whereby the breakdown strength of said PN junction is relatively high, said juNction having a boundary which intercepts said surface, at least one diffused diode region, of said opposite type conductivity, in said body adjacent to said surface in overlapping relation to a portion of said boundary of said gradual PN junction and itself defining an abrupt PN junction of relatively low breakdown strength with the material of said body, and spaced conductors coupled to said resistor region for connecting said resistor to other elements of said device.
Claim 2
Dependent Claim
255 words
In a semiconductor device of the type which has a body of semiconductive material of one type and degree of conductivity and which further has a plurality of diffused regions in said body adjacent to a surface thereof for defining active and passive circuit elements including a pair of insulated gate field effect transistors, one of which has spaced source and drain regions in said body adjacent to said surface and the other having a diffused well region of conductivity type opposite to that of said body in said body adjacent to said surface and a pair of source and drain regions of said one type conductivity within said well region, resistor and diode elements characterized by relatively high resistance and relatively low diode breakdown strength, respectively, comprising: a diffused resistor region, of said opposite type conductivity and having the same depth and impurity concentration gradient as said diffused well region, in said body adjacent to said surface and defining a gradual PN junction in said body, whereby the breakdown strength of said PN junction is relatively high, said juNction having a boundary which intercepts said surface, at least one diffused diode region, of said opposite type conductivity, in said body adjacent to said surface in overlapping relation to a portion of said boundary of said gradual PN junction and itself defining an abrupt PN junction of relatively low breakdown strength with the material of said body, and spaced conductors coupled to said resistor region for connecting said resistor to other elements of said device.
Claim 3
Dependent Claim
44 words
A semiconductor device as defined in claim 1 wherein said resistor region has the plan configuration of an elongated rectangle having a pair of relatively long sides and a pair of relatively short ends, said diode region being located at one of said ends.
Claim 4
Dependent Claim
22 words
A semiconductor device as defined in claim 2, further comprising: a second diode region located at the other of said resistor ends.
Claim 5
Dependent Claim
41 words
A semiconductor device as defined in claim 2, further comprising: a diffused region of the same type conductivity as said body in said body adjacent to said surface in overlapping relation to a portion of a side of said resistor region.
Claim 6
Dependent Claim
24 words
A semiconductor device as defined in claim 1 wherein one of said spaced conductors includes a metal electrode in contact with said diode region.
Claim 7
Dependent Claim
48 words
A semiconductor device as defined in claim 1 wherein there are at least two diffused diode regions each in overlapping relation to a different portion of said boundary of said gradual PN junction, and wherein said spaced conductors include metal electrodes in contact with both said diode regions.
Claim 8
Dependent Claim
129 words
A CMOS integrated circuit device comprising: a body of semiconductive material of one type conductivity having a surface, a diffused well region of predetermined resistivity, and conductivity type opposite to that of said body, in said body adjacent to said surface, spaced source and drain regions of said one type conductivity within said diffused region adjacent to said surface, spaced source and drain regions of said opposite type conductivity outside of said diffused region adjacent to said surface, a gate electrode over the spaced between each pair of source and drain regions and separated therefrom by an insulator, and a resistor region of said opposite type conductivity in said body adjacent to said surface, said resistor region having the same resistivity and impurity concentration gradient as said well region.
Claim 9
Dependent Claim
129 words
A CMOS integrated circuit device comprising: a body of semiconductive material of one type conductivity having a surface, a diffused well region of predetermined resistivity, and conductivity type opposite to that of said body, in said body adjacent to said surface, spaced source and drain regions of said one type conductivity within said diffused region adjacent to said surface, spaced source and drain regions of said opposite type conductivity outside of said diffused region adjacent to said surface, a gate electrode over the spaced between each pair of source and drain regions and separated therefrom by an insulator, and a resistor region of said opposite type conductivity in said body adjacent to said surface, said resistor region having the same resistivity and impurity concentration gradient as said well region.
Claim 10
Dependent Claim
48 words
A CMOS integrated circuit device as defined in claim 7 wherein said device has input terminals and said resistor region has spaced contacts thereto, one of said contacts being coupled to one of said input terminals and the other of said contacts being connected to a gate electrode.
Claim 11
Dependent Claim
49 words
A CMOS integrated circuit device as defined in claim 8 further comprising: a diffused region of said opposite type conductivity in said body adjacent to said surface having a resistivity such that an abrupt, low breakdown PN junction is defined, and means coupling said region to said resistor region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-06-27 | 1975-12-27 | 1976-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-06-27 | 1979-12-27 | 1980-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-06-27 | 1983-12-27 | 1984-06-27 | $7700.00 | Window Closed / Lapsed |