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US3688264A
Expired / Lapsed
US
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Operation of field-effect transistor circuits having substantial distributed capacitance
Assignee: Harris Semiconductor Patents Inc
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Filing: 1971-04-22
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Granted: 1972-08-29
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Expires: 1991-04-22
Abstract
Abstract The distributed capacitance at circuit node between conduction paths of interconnected field-effect transistors of a memory array is maintained charged to a fixed value during the major portion of the memory operating time. As one example, the distributed capacitance at the columns of an integrated circuit of a memory chip may be connected to the charging source except for the times during which any location on that chip is being accessed. Operation in this way opens sneak paths in the circuit and reduces power dissipation.
Inventors
- 👤 Andrew G F Dingwall
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 18:06
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C11/413; G11C11/417; G11C11/419; H03K17/00; H03K17/04; H03K17/041; H03K17/04106
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
164 words
In a field-effect transistor memory array, in combination: a plurality of groups of field-effect transistor storage cells; a plurality of circuit nodes coupled to said groups of said storage cells, each node exhibiting distributed capacitance; a plurality of charging means, one such means for each group of cells, each means coupled to the nodes for a different group of cells, each means for normally maintaining the capacitance at the nodes to which it is connected charged to a reference value; cell selection means for selecting a desired one of said cells comprising normally open switch means connecting a circuit node to said cell, and means responsive to a control signal calling for the selection of a group of cells and a select signal manifestation calling for a cell within that group for closing said switch means; and means responsive to said signal calling for the selection of a group of cells for disconnecting said charging means from the nodes for that group of cells.
Claim 2
Dependent Claim
164 words
In a field-effect transistor memory array, in combination: a plurality of groups of field-effect transistor storage cells; a plurality of circuit nodes coupled to said groups of said storage cells, each node exhibiting distributed capacitance; a plurality of charging means, one such means for each group of cells, each means coupled to the nodes for a different group of cells, each means for normally maintaining the capacitance at the nodes to which it is connected charged to a reference value; cell selection means for selecting a desired one of said cells comprising normally open switch means connecting a circuit node to said cell, and means responsive to a control signal calling for the selection of a group of cells and a select signal manifestation calling for a cell within that group for closing said switch means; and means responsive to said signal calling for the selection of a group of cells for disconnecting said charging means from the nodes for that group of cells.
Claim 3
Dependent Claim
128 words
In an integrated circuit memory system which includes a plurality of memory chips, each chip comprising an array of field-effect transistor memory cells, each column of each memory array exhibiting substantial distributed capacitance, and further including for each array charging means connected to said columns of said array for normally maintaining the distributed capacitances of that array charged to a reference level, the improvement comprising: means for accessing a memory cell on one of said chips comprising means for applying to that chip a chip select signal and for applying to the desired cell on that chip a row select signal and a column select signal; and means responsive to said chip select signal for disconnecting said charging means for said chip from the columns of that chip.
Claim 4
Dependent Claim
128 words
In an integrated circuit memory system which includes a plurality of memory chips, each chip comprising an array of field-effect transistor memory cells, each column of each memory array exhibiting substantial distributed capacitance, and further including for each array charging means connected to said columns of said array for normally maintaining the distributed capacitances of that array charged to a reference level, the improvement comprising: means for accessing a memory cell on one of said chips comprising means for applying to that chip a chip select signal and for applying to the desired cell on that chip a row select signal and a column select signal; and means responsive to said chip select signal for disconnecting said charging means for said chip from the columns of that chip.
Claim 5
Dependent Claim
61 words
In the memory system as set forth in claim 2, said means for accessing a location comprising logic gate means for each row of the memory responsive to the concurrent presence of a row select signal manifestation and said chip select signal, for applying said select signal to all cells of a row only when a chip select signal is present.
Claim 6
Dependent Claim
30 words
In the memory system as set forth in claim 2, said last named means comprising field-effect transistors whose conduction paths are connected between said charging means and the respective columns.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-08-29 | 1976-02-28 | 1976-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-08-29 | 1980-02-28 | 1980-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-08-29 | 1984-02-28 | 1984-08-29 | $7700.00 | Window Closed / Lapsed |