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US3700780A Expired / Lapsed US ⏱️ 0.0 years remaining

Dual delayed sequence generator with read only memory control for 256 output triples for plane and spherical wave-front simulations

Assignee: United States Department of the Navy
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Filing: 1971-05-04
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Granted: 1972-10-24
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Expires: 1991-05-04
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Abstract

Abstract A dual delayed sequence digital generator having a plurality of shift register modules connected to generate linear sequences, each module stage having an output to a solid state switch under the control of a read only memory (ROM) circuit to switch the shift register outputs to a combination of OR gates operating in a modulo-2 manner to sift all shift register outputs to a single digital output through a filter, limiter and buffer, the combination of similar circuits providing a plurality of delayed signals simulating a sonar signal wavefront from a simulated target in inner space.

Inventors

  • 👤 Eugene R Roeschlein

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 05:52
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/58; G06F7/582; G06F7/584; G01; G01S; G01S7/00; G01S7/02; G01S7/40; G09; G09B; G09B9/00; G09B9/56; G06F2207/00; G06F2207/58; G06F2207/581; G06F2207/583

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 369 words
A dual delayed sequence generator for producing different sonar wavefront simulations comprising: a shift register of a plurality of multibit flatpac stages, each stage having an output with a predetermined combination of stage outputs coupled through exclusive OR gates to the first stage input as a feedback to establish a predetermined linear sequence of bits through said shift register providing an original sequence or reference delay on said stage outputs; a clock pulse source coupled in common to said shift register stages to drive same to shift the feedback input therethrough; a NAND gate switch coupled one each to one each shift register stage output, each gate switch having a gating input and an output; a read only memory having a plurality of outputs, one each output being coupled to one each NAND gate switch gating input, and said read only memory having a plurality of control inputs; a counter circuit having a plurality of outputs coupling said plurality of inputs of said read only memory, combinations of said counter circuit outputs being selectable to produce selected outputs of said read only memory to produce selected outputs from said NAND gate switches to select and gate through the aforementioned linear sequence as it appears at the various shift register stage outputs; a multiple exclusive OR circuit with the NAND gate switch outputs coupled to a modulo-2 manner through the circuit to a single output to reproduce the sequence of said shift register to any desired delay with respect to the reference sequence of the original shift register and thus to simulate a sonar signal received from one sonar microphone, said NAND gate switches, read only memory, and multiple exclusive OR circuit being repeated in modular form and coupled to said original shift register and counter circuit to simulate sonar signals received at other sonar microphones with different time delays to simulate wavefronts from a target to position same; and a signal conditioner coupled to said multiple exclusive OR circuit output to provide spectral shaping of these delayed signals and the combination of said repeated circuits provides simulated signals from a plurality of simulated sonar receiver microphones to establish a simulated wavefront from a simulated target object in inner space.
Claim 2
Dependent Claim 369 words
A dual delayed sequence generator for producing different sonar wavefront simulations comprising: a shift register of a plurality of multibit flatpac stages, each stage having an output with a predetermined combination of stage outputs coupled through exclusive OR gates to the first stage input as a feedback to establish a predetermined linear sequence of bits through said shift register providing an original sequence or reference delay on said stage outputs; a clock pulse source coupled in common to said shift register stages to drive same to shift the feedback input therethrough; a NAND gate switch coupled one each to one each shift register stage output, each gate switch having a gating input and an output; a read only memory having a plurality of outputs, one each output being coupled to one each NAND gate switch gating input, and said read only memory having a plurality of control inputs; a counter circuit having a plurality of outputs coupling said plurality of inputs of said read only memory, combinations of said counter circuit outputs being selectable to produce selected outputs of said read only memory to produce selected outputs from said NAND gate switches to select and gate through the aforementioned linear sequence as it appears at the various shift register stage outputs; a multiple exclusive OR circuit with the NAND gate switch outputs coupled to a modulo-2 manner through the circuit to a single output to reproduce the sequence of said shift register to any desired delay with respect to the reference sequence of the original shift register and thus to simulate a sonar signal received from one sonar microphone, said NAND gate switches, read only memory, and multiple exclusive OR circuit being repeated in modular form and coupled to said original shift register and counter circuit to simulate sonar signals received at other sonar microphones with different time delays to simulate wavefronts from a target to position same; and a signal conditioner coupled to said multiple exclusive OR circuit output to provide spectral shaping of these delayed signals and the combination of said repeated circuits provides simulated signals from a plurality of simulated sonar receiver microphones to establish a simulated wavefront from a simulated target object in inner space.
Claim 3
Dependent Claim 51 words
A dual delayed sequence generator as set forth in claim 1 wherein said counter circuit outputs are selectable from a plurality of programs to program said read only memory to establish different combinations of gating signals to said NAND gate switches to estAblish different sonar wavefronts fixing different simulated target positions.
Claim 4
Dependent Claim 33 words
A dual delayed sequence generator as set forth in claim 2 wherein said clock pulse source is adjustable in frequency to increase and decrease signal delays corresponding to different sound velocities in water.
Claim 5
Dependent Claim 80 words
A dual delayed sequence generator as set forth in claim 3 wherein said predetermined combination of stage outputs from said shift register consists of four stage outputs in two pairs of two each, each pair being coupled to one of said exclusive OR gates and the outputs of both pairs of exclusive OR gates being coupled to a third exclusive OR gate, the output thereof being said feedback into said first stage, thus generating the original or reference linear sequence.
Claim 6
Dependent Claim 68 words
A dual delayed sequence generator as set forth in claim 4 wherein said shift register consists of a plurality of multiple stages, each stage having a plurality of bit counts providing a shift register of 2N-1 sequence states, where N is the number of multiple stages, and the number of outputs of said read only memory and the number of NAND gate switches correspond to this number N.
Claim 7
Dependent Claim 53 words
A dual delayed sequence generator as set forth in claim 5 wherein said signal conditioner includes a filter to control the spectral density of the output signal, a limiter to convert the output signals to the desired digital bandwidth, and a buffer amplifier to enable the signal output to drive a signal load.
Claim 8
Dependent Claim 48 words
A dual delayed sequence generator as set forth in claim 6 wherein said signal conditioner includes multiple inputs to permit additional similarly generated simulated targets and an input from noise generators to provide for noise to be added for various signal to noise ratios of these simulated targets.
Claim 9
Dependent Claim 44 words
A dual delayed sequence generator as set forth in claim 7 wherein said target simulation may be made to cyclically move through a predetermined path relative to own ship motion and this may be extended to simulate a number of targets simultaneously in motion.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-10-24 1976-04-24 1976-10-24 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-10-24 1980-04-24 1980-10-24 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-10-24 1984-04-24 1984-10-24 $7700.00 Window Closed / Lapsed

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