Patent US3701142A successfully refreshed from Google Patents.
US3701142A
Expired / Lapsed
US
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Integrating converters with synchronous starting
Assignee: G DEAN MCADOO Inc A CORP OF NJ
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Filing: 1970-03-30
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Granted: 1972-10-24
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Expires: 1990-03-30
Abstract
Abstract A circuit provides a reset and start pulse synchronized with a clock pulse for accurate starting and timing of the integrating process in a conventional dual-slope converter. A cycle flip-flop is randomly set to a logical one state to enable a gate to pass the next inverted pulse from a clock. Further pulses are inhibited from passing through the gate by an inhibit signal generated by a toggling flip-flop responsively to the trailing edge of the gate output pulse. The leading edge of the gate output pulse is used to reset the counter to zero, to start the integrating process and to open a gate to pass clock pulses to the counter, all substantially coincident with the first negative transition of a clock pulse following the setting of the cycle flip-flop to its logical one state.
Inventors
- 👤 Alexander B Cannara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:07
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/50; H03M1/52
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
121 words
In an integrating converter having a clock for generating a timing signal characterized by successive clock pulses, means for generating a starting control pulse synchronized with a clock pulse in response to a random start signal, comprising: a. signal gating means, b. means for applying said timing signal to said signal gating means, c. means actuated by said random start signal for enabling said signal gating means in response to a first clock pulse to pass the first clock pulse to provide said starting control pulse, and d. means actuated by said random start signal for inhibiting said signal gating means in response to said starting control pulse to inhibit any further clock pulses from passing through said signal gating means.
Claim 2
Dependent Claim
121 words
In an integrating converter having a clock for generating a timing signal characterized by successive clock pulses, means for generating a starting control pulse synchronized with a clock pulse in response to a random start signal, comprising: a. signal gating means, b. means for applying said timing signal to said signal gating means, c. means actuated by said random start signal for enabling said signal gating means in response to a first clock pulse to pass the first clock pulse to provide said starting control pulse, and d. means actuated by said random start signal for inhibiting said signal gating means in response to said starting control pulse to inhibit any further clock pulses from passing through said signal gating means.
Claim 3
Dependent Claim
92 words
The apparatus defined in claim 1 wherein said means for enabling said signal gating means comprises: a. a flip-flop circuit having preset and toggle input terminals for producing a gate enabling signal in response to the signal applied to said toggle input terminal when preset by the signal applied to said preset terminal, b. means for applying said random start signal to said preset input terminal, c. means for applying said timing signal to said toggle input terminal, and d. means for applying said gate enabling signal to said signal gating means.
Claim 4
Dependent Claim
99 words
The apparatus defined in claim 1 wherein said means for inhibiting said signal gating means comprises: a. a flip-flop circuit having preset and toggle input terminals for producing a gate inhibiting signal in response to the signal applied to said toggle input terminal when preset by the signal applied to said preset input terminal, b. means for applying said random start signal to said preset input terminal, c. means for applying said control pulse passed by said signal gating means to said toggle input terminal, and d. means for applying said gate inhibiting signal to said signal gating means.
Claim 5
Dependent Claim
137 words
In an integrating converter having pulse timing means, integrating means and digital counting means, means for generating a starting control pulse synchronized with a timing pulse, comprising: a. a clock for generating clock pulses having a 50 percent duty cycle, b. a first flip-flop controlled By a random input signal to provide a logical one output signal, c. a second flip-flop preset by said first flip-flop and controlled by said clock, d. an AND gate having three inputs connected to receive respectively an inverted clock signal, and the outputs of the first and second flip-flops, e. a third flip-flop preset by said first flip-flop and controlled by the output of said AND gate, and f. means connecting the output of said third flip-flop to a fourth input of said AND gate to provide an inhibit signal thereto.
Claim 6
Dependent Claim
137 words
In an integrating converter having pulse timing means, integrating means and digital counting means, means for generating a starting control pulse synchronized with a timing pulse, comprising: a. a clock for generating clock pulses having a 50 percent duty cycle, b. a first flip-flop controlled By a random input signal to provide a logical one output signal, c. a second flip-flop preset by said first flip-flop and controlled by said clock, d. an AND gate having three inputs connected to receive respectively an inverted clock signal, and the outputs of the first and second flip-flops, e. a third flip-flop preset by said first flip-flop and controlled by the output of said AND gate, and f. means connecting the output of said third flip-flop to a fourth input of said AND gate to provide an inhibit signal thereto.
Claim 7
Dependent Claim
111 words
In an integrating converter having a clock, an analog signal integrator and a digital counter, means for starting the analog signal integrator and the digital counter in synchronization with said clock to improve the accuracy of the converter comprising: a. a clock for generating clock pulses, b. means actuated responsively to a random start signal to generate a control signal synchronous with a clock pulse, c. means actuated responsively to the control signal for resetting the counter, d. gate means opened responsively to the control signal for passing clock pulses to the counter, and e. means actuated responsively to the control signal for enabling the integrator to begin the integration process.
Claim 8
Dependent Claim
111 words
In an integrating converter having a clock, an analog signal integrator and a digital counter, means for starting the analog signal integrator and the digital counter in synchronization with said clock to improve the accuracy of the converter comprising: a. a clock for generating clock pulses, b. means actuated responsively to a random start signal to generate a control signal synchronous with a clock pulse, c. means actuated responsively to the control signal for resetting the counter, d. gate means opened responsively to the control signal for passing clock pulses to the counter, and e. means actuated responsively to the control signal for enabling the integrator to begin the integration process.
Claim 9
Dependent Claim
98 words
The apparatus defined in claim 5 wherein said means actuated responsively to a random start signal to generate a control signal comprises: a. signal gating means b. means for applying a signal representative of the clock pulses to said signal gating means, c. means actuated by the random start signal for enabling the signal gating means in response to a first clock pulse to pass the signal representative of the clock pulses to provide the control signal, and d. means actuated by the random start signal for inhibiting the signal gating means in response to the control signal.
Claim 10
Dependent Claim
93 words
The apparatus defined in claim 6 wherein said means for enabling the signal gating means comprises: a. a flip-flop circuit having preset and toggle input terminals for producing a gate enabling signal in response to the signal applied to the toggle input terminal when preset by the signal applied to the preset input terminal, b. means for applying the random start signal to the preset input terminal, c. means for applying the clock pulses to the toggle input terminal, and d. means for applying the gate enabling signal to the signal gating means.
Claim 11
Dependent Claim
28 words
The apparatus defined in claim 7 wherein said flip-flop circuit is responsive to the trailing edge of a pulse in the signal applied to said toggle input terminal.
Claim 12
Dependent Claim
99 words
The apparatus defined in claim 6 wherein said means for inhibiting the signal gating means comprises: a. a flip-flop circuit having preset and toggle input terminals for producing a gate inhibiting signal in response to the signal applied to the toggle input terminal when preset by the signal applied to the preset input terminal, b. means for applying the random start signal to the preset input terminal, c. means for applying the control signal passed by the signal gating means to the toggle input terminal, and d. means for applying the gate inhibiting signal to the signal gating means.
Claim 13
Dependent Claim
28 words
The apparatus defined in claim 9 wherein said flip-flop circuit is responsive to the trailing edge of a pulse in the signal applied to said toggle input terminal.
Claim 14
Dependent Claim
116 words
The apparatus defined in claim 5 wherein said means actuated responsively to a random start signal to generate a control signal comprises: a. signal gating means, b. signal inverter means for applying a signal representative of the logical inverse of the clock pulses to said signal gating means, c. means actuated by the random start signal for enabling the signal gating means in response to a first clock pulse to pass the inverted clock pulse signal to provide the control signal, and d. means actuated by the random start signal for inhibiting the signal gating means in response tO the control signal to prevent any further inverted clock pulses from passing through said signal gating means.
Claim 15
Dependent Claim
98 words
The apparatus defined in claim 11 wherein said means for enabling the signal gating means comprises: a. a flip-flop circuit having preset and toggle input terminals for producing a gate enabling signal in response to the trailing edge of a signal pulse applied to the toggle input terminal when preset by the signal applied to the preset input terminal, b. means for applying the random start signal to the preset input terminal, c. means for applying the clock pulses to the toggle input terminal, and d. means for applying the gate enabling signal to the signal gating means.
Claim 16
Dependent Claim
104 words
The apparatus defined in claim 11 wherein said means for inhibiting the signal gating means comprises: a. a flip-flop circuit having preset and toggle input terminals for producing a gate inhibiting signal in response to the trailing edge of a signal pulse applied to the toggle input terminal when preset by the signal applied to the preset input terminal, b. means for applying the random start signal to the preset input terminal, c. means for applying the control pulse passed by the signal gating means to the toggle input terminal, and d. means for applying the gate inhibiting signal to the signal gating means.
Claim 17
Dependent Claim
152 words
In an integrating converter having a clock for generating clock pulses, an analog signal integrator and a digital counter, means for providing synchronous starting of the integration process to improve the accuracy of the converter comprising: a. signal gating means for selectively applying said clock pulses to said counter, b. a flip-flop having an input and an output, c. means for randomly applying a start signal to said input to establish a logical one signal at said output, d. gate means actuated responsively to said logical output signal to pass a clock pulse to an output line to provide a control pulse, e. means actuated responsively to the trailing edge of said control pulse to inhibit passage of further clock pulses to the output line, and f. means actuated responsively to the leading edge of the control pulse for enabling said integrator and said signal gating means in synchronization with said clock.
Claim 18
Dependent Claim
152 words
In an integrating converter having a clock for generating clock pulses, an analog signal integrator and a digital counter, means for providing synchronous starting of the integration process to improve the accuracy of the converter comprising: a. signal gating means for selectively applying said clock pulses to said counter, b. a flip-flop having an input and an output, c. means for randomly applying a start signal to said input to establish a logical one signal at said output, d. gate means actuated responsively to said logical output signal to pass a clock pulse to an output line to provide a control pulse, e. means actuated responsively to the trailing edge of said control pulse to inhibit passage of further clock pulses to the output line, and f. means actuated responsively to the leading edge of the control pulse for enabling said integrator and said signal gating means in synchronization with said clock.
Claim 19
Dependent Claim
32 words
The apparatus defined in claim 14 wherein said means for enabling said integrator and said signal gating means in synchronization with said clock simultaneously enables said integrator and said signal gating means.
Claim 20
Dependent Claim
23 words
The apparatus defined in claim 14 further comprising means actuated responsively to the leading edge of the control pulse for resetting said counter.
Claim 21
Dependent Claim
130 words
In an integrating converter having a clock for generating a timing signal characterized by successive clock pulses, means for generating a starting control pulse synchronized with a clock pulse in response to a random start signal, comprising: a. signal gating means, b. signal inverter means for applying a signal representative of the logical inverse of said timing signal to said signal gating means, c. means actuated by said random start signal for enabling said signal gating means in response to a first clock pulse to pass the first inverted clock pulse to provide said starting control pulse, and d. means actuated by said random start signal for inhibiting said signal gating means in response to said starting control pulse to inhibit any further clock pulses from passing through said gate.
Claim 22
Dependent Claim
130 words
In an integrating converter having a clock for generating a timing signal characterized by successive clock pulses, means for generating a starting control pulse synchronized with a clock pulse in response to a random start signal, comprising: a. signal gating means, b. signal inverter means for applying a signal representative of the logical inverse of said timing signal to said signal gating means, c. means actuated by said random start signal for enabling said signal gating means in response to a first clock pulse to pass the first inverted clock pulse to provide said starting control pulse, and d. means actuated by said random start signal for inhibiting said signal gating means in response to said starting control pulse to inhibit any further clock pulses from passing through said gate.
Claim 23
Dependent Claim
92 words
The apparatus defined in claim 17 wherein said means for enabling said signal gating means comprises: a. a flip-flop circuit having preset and toggle input terminals for producing a gate enabling signal in response to the signal applied to said toggle input terminal when preset by the signal applied to said preset terminal, b. means for applying said random start signal to said preset input terminal, c. means for applying said timing signal to said toggle input terminal, and d. means for applying said gate enabling signal to said signal gating means.
Claim 24
Dependent Claim
28 words
The apparatus defined in claim 18 wherein said flip-flop circuit is responsive to the trailing edge of a pulse in the signal applied to said toggle input terminal.
Claim 25
Dependent Claim
99 words
The apparatus defined in claim 17 wherein said means for inhibiting said signal gating means comprises: a. a flip-flop circuit having preset and toggle input terminals for producing a gate inhibiting signal in response to the signal applied to said toggle input terminal when preset by the signal applied to said preset input terminal, b. means for applying said random start signal to said preset input terminal, c. means for applying said control pulse passed by said signal gating means to said toggle input terminal, and d. means for applying said gate inhibiting signal to said signal gating means.
Claim 26
Dependent Claim
28 words
The apparatus defined in claim 20 wherein said flip-flop circuit is responsive to the trailing edge of a pulse in the signal applied to said toggle input terminal.
Claim 27
Dependent Claim
108 words
In an integrating converter having a clock for generating clock pulses, an analog signal integrator and a digital counter, apparatus for improving the accuracy of said converter comprising: a. switching means for selectively enabling said analog signal integrator, b. signal gating means for selectively applying said clock pulses to said counter, c. means responsive to a random starting signal for generating a control pulse synchronized with a clock pulse, and d. means responsive to the leading edge of said control pulse for enabling said switching means and said signal gating means to start said analog signal integrator and said digital counter simultaneously and in synchronization with said clock.
Claim 28
Dependent Claim
108 words
In an integrating converter having a clock for generating clock pulses, an analog signal integrator and a digital counter, apparatus for improving the accuracy of said converter comprising: a. switching means for selectively enabling said analog signal integrator, b. signal gating means for selectively applying said clock pulses to said counter, c. means responsive to a random starting signal for generating a control pulse synchronized with a clock pulse, and d. means responsive to the leading edge of said control pulse for enabling said switching means and said signal gating means to start said analog signal integrator and said digital counter simultaneously and in synchronization with said clock.
Claim 29
Dependent Claim
22 words
The apparatus defined in claim 22 further comprising means responsive to the leading edge of said control pulse for resetting said counter.
Claim 30
Dependent Claim
150 words
Apparatus for digitally timing an analog signal process comprising: a. a block for producing a timing signal alternating between first and second logical levels for substantially equal time intervals, b. signal gating means responsive to said timing signal for producing an output signal having the logical level of said timing signal when enabled and having said first logical level when disabled, c. counting means responsive to the output signal of said signal gating means for counting changes in the level of said output signal from said second logical level to said first logical level, d. means responsive to a random start signal for generating a control pulse synchronous with said timing signal, e. means responsive to said control pulse for simultaneously starting said analog signal process and enabling said signal gating means, and f. means responsive to the completion of said analog signal process for disabling said signal gating means.
Claim 31
Dependent Claim
150 words
Apparatus for digitally timing an analog signal process comprising: a. a block for producing a timing signal alternating between first and second logical levels for substantially equal time intervals, b. signal gating means responsive to said timing signal for producing an output signal having the logical level of said timing signal when enabled and having said first logical level when disabled, c. counting means responsive to the output signal of said signal gating means for counting changes in the level of said output signal from said second logical level to said first logical level, d. means responsive to a random start signal for generating a control pulse synchronous with said timing signal, e. means responsive to said control pulse for simultaneously starting said analog signal process and enabling said signal gating means, and f. means responsive to the completion of said analog signal process for disabling said signal gating means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-24 | 1976-04-24 | 1976-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-24 | 1980-04-24 | 1980-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-24 | 1984-04-24 | 1984-10-24 | $7700.00 | Window Closed / Lapsed |