Functional memory storage cell

Claim 2

A fOur state cell for a functional memory characterized by concurrent writing of two binary bits of data into and concurrent reading of two binary bits of data out of the memory, said cell comprising a pair of latches each having an input and an output; each latch including a first series circuit having a first pair of complementary insulated gate field effect transistors, a second series circuit having a second pair of complementary insulated gate field effect transistors, means for connecting the first and second series circuits in parallel with each other, the connection between the first pair of transistors being connected to the gate electrodes of the second pair of transistors to provide feedback, and the connection between the second pair of transistors being connected to the gate electrodes of the first pair of transistors to provide feedback; only one pair of data input-search-output lines; a write enable line adapted to receive write enable signals; a word line adapted to receive read signals; first and second write-gate insulated gate field effect transistors, each having its gate electrode coupled to the write enable line and responsive to write enable signals applied thereto for coupling one and the other of the data lines respectively to the inputs of one of the other of the latches to set the latches in states corresponding to the input data signals on the lines; and first and second read-gate insulated gate field effect transistors, each having its gate electrode coupled to the output of a respective one of the latches and responsive to the state of the respective latch for alternatively coupling or blocking the coupling of the word line to a respective one of the data lines, whereby read signals applied to the word line during read cycles are selectively applied to or blocked from the data lines to read out the state of the cell and whereby search signals applied to the data lines during search/select cycles are selectively applied to or blocked from the word line to indicate search-data/cell-state match and mismatch conditions.

Claim 3

The combination of claim 1 wherein the first and second pairs of transistors are complementary and are operated in the enhancement mode.

Claim 4

The cell set forth in claim 1 further comprising a pair of isolation transistors of the insulated gate field effect transistor type each responsive to write enable signals for isolating a respective latch input from feedback connections thereby minimizing input drive requirements to the cell.

Claim 5

The cell set forth in claim 1 further comprising a read line adapted to receive read-gate signals third and fourth read-gate insulated gate field effect transistors, each interposed between a respective one of the data lines and a respective one of the first and second read-gate transistors and each having its gate electrode connected to the read line and responsive to read-gate signals for coupling the respective data line to the word line by way of the respective one of the first and second read-gate transistors.

Claim 6

The cell set forth in claim 4 further comprising an additional pair of insulated gate field effect transistors having their gate electrodes coupled to respective ones of the data lines and responsive to signals on said lines during search/select cycles to selectively couple mismatch signals to the word line by way of respective ones of said third and fourth read-gate transistors.

Claim 7

A four state cell for a functional memory, said cell comprising a pair of latches each having an input and an output; each latch including a first series circuit having a first pair of insulated gate field effect transistors, a second series circuit having a second pair of insulated gate field effect transistors, means for connecting the first and second series circuits in parallel with each other, the connection between the first pair of transistors being connected to the gate electrodes oF the second pair of transistors to provide feedback, and the connection between the second pair of transistors being connected to the gate electrodes of the first pair of transistors to provide feedback; only one pair of data lines; a write enable line adapted to receive write enable signals; a word line adapted to receive read signals; first and second write-gate insulated gate field effect transistors each having its gate electrode coupled to the write enable line and responsive to write enable signals applied thereto for coupling one and the other of the data lines respectively to the inputs of one and the other of the latches to set the latches in states corresponding to the input data signals on the lines; and first and second read gate insulated gate field effect transistors each having its gate electrode coupled to the output of a respective one of the latches and responsive to the state of the respective latch for alternatively coupling or blocking the coupling of the word line to a respective one of the data lines.

Claim 8

A four state cell for a functional memory, said cell comprising a pair of latches each having an input and an output; each latch including a first series circuit having a first pair of insulated gate field effect transistors, a second series circuit having a second pair of insulated gate field effect transistors, means for connecting the first and second series circuits in parallel with each other, the connection between the first pair of transistors being connected to the gate electrodes oF the second pair of transistors to provide feedback, and the connection between the second pair of transistors being connected to the gate electrodes of the first pair of transistors to provide feedback; only one pair of data lines; a write enable line adapted to receive write enable signals; a word line adapted to receive read signals; first and second write-gate insulated gate field effect transistors each having its gate electrode coupled to the write enable line and responsive to write enable signals applied thereto for coupling one and the other of the data lines respectively to the inputs of one and the other of the latches to set the latches in states corresponding to the input data signals on the lines; and first and second read gate insulated gate field effect transistors each having its gate electrode coupled to the output of a respective one of the latches and responsive to the state of the respective latch for alternatively coupling or blocking the coupling of the word line to a respective one of the data lines.

Claim 9

The combination of claim 6 wherein the first and second pairs of transistors are complementary and are operated in the enhancement mode.

Claim 10

The combination of claim 6 further comprising a pair of supply terminals, and said first and second series circuits being connected in parallel between said terminals.

Claim 11

The cell set forth in claim 6 further comprising a pair of isolation transistors of the insulated gate field effect transistor type each responsive to write enable signals for isolating a respective latch input from feedback connections thereby minimizing input drive requirements to the cell.

Claim 12

The cell set forth in claim 6 further comprising a read line adapted to receive read-gate signals third and fourth read-gate insulated gate field effect transistors, each interposed between a respective one of the data lines and a respective one of the first and second read-gate transistors and each having its gate electrode connected to the read line and responsive to read-gate signals for coupling the respective data line to the word line by way of the respective one of the first and second read-gate transistors.

Claim 13

A four state cell for a functional memory characterized by concurrent writing of pairs of binary bits of data into and concurrent reading of pairs of binary bits of data out of the memory, said cell comprising a pair of latches each having an input and an output; each latch including first and second pairs of series-connected insulated gate field effect transistors cross-coupled to provide a latching function; only one pair of data input-search-output lines; a write enable line adapted to receive write enable signals; a word line adapted to receive read signals; first and second write-gate insulated gate field effect transistors each having its gate electrode coupled to the write enable line and responsive to write enable signals applied thereto for coupling one and the other of the data lines respectively to the inputs of one and the other of the latches to set the latches in states corresponding to the input data signals on the lines; and first and second read-gate insulated gate field effect transistors each having its gate electrode coupled to the output of a respective one of the latches and responsive to the state of the respective latch for alternatively coupling or blocking the coupling of the word line to a respective one of the data lines, whereby read signals applied to the word line during read cycles are selectively applied to or blocked from the data lines to read out the state of the cell and whereby search signals applied to the data lines during search/select cycles are selectively applied to or blocked from the word line to indicate search data-cell state match and mismatch conditions.

Claim 14

A four state cell for a functional memory characterized by concurrent writing of pairs of binary bits of data into and concurrent reading of pairs of binary bits of data out of the memory, said cell comprising a pair of latches each having an input and an output; each latch including first and second pairs of series-connected insulated gate field effect transistors cross-coupled to provide a latching function; only one pair of data input-search-output lines; a write enable line adapted to receive write enable signals; a word line adapted to receive read signals; first and second write-gate insulated gate field effect transistors each having its gate electrode coupled to the write enable line and responsive to write enable signals applied thereto for coupling one and the other of the data lines respectively to the inputs of one and the other of the latches to set the latches in states corresponding to the input data signals on the lines; and first and second read-gate insulated gate field effect transistors each having its gate electrode coupled to the output of a respective one of the latches and responsive to the state of the respective latch for alternatively coupling or blocking the coupling of the word line to a respective one of the data lines, whereby read signals applied to the word line during read cycles are selectively applied to or blocked from the data lines to read out the state of the cell and whereby search signals applied to the data lines during search/select cycles are selectively applied to or blocked from the word line to indicate search data-cell state match and mismatch conditions.

Claim 15

The cell set forth in claim 11 wherein the transistors are complementary P channel and N channel devices operated in The enhancement mode, said cell further comprising a pair of terminals adapted for connection to differential potentials of a power supply, and means connecting the series connected transistors between said terminals.

Claim 16

A four state cell for a functional memory characterized by concurrent writing of pairs of binary bits of data into and concurrent reading of pairs of binary bits of data out of the memory, said cell comprising a pair of latches each having an input and an output; each latch including first and second pairs of series-connected insulated gate field effect transistors cross-coupled to provide a latching function; only one pair of data input-search-output lines; a write enable line adapted to receive write enable signals; a word line and a read line, each adapted to receive read signals; first and second write-gate insulated gate field effect transistors each having its gate electrode coupled to the write enable line and responsive to write enable signals for coupling one and the other of the data lines respectively to the inputs of one and the other of the latches to set the latches in states corresponding to the input data signals on the lines; and first and second read-gate insulated gate field effect transistors each having its gate electrode coupled to the output of a respective one of the latches and responsive to the state of the respective latch for alternatively preparing the coupling or blocking the coupling of the word line to a respective one of the data lines, third and fourth read-gate insulated gate field effect transistors each having its gate electrode coupled to the read line and responsive to read signals for coupling the word line to a respective one of the data lines by way of a respective one of the first and second read-gate transistors, whereby read signals applied to the word line during read cycles are selectively applied to or blocked from the data lines to read out the state of the cell.

Claim 17

A four state cell for a functional memory characterized by concurrent writing of pairs of binary bits of data into and concurrent reading of pairs of binary bits of data out of the memory, said cell comprising a pair of latches each having an input and an output; each latch including first and second pairs of series-connected insulated gate field effect transistors cross-coupled to provide a latching function; only one pair of data input-search-output lines; a write enable line adapted to receive write enable signals; a word line and a read line, each adapted to receive read signals; first and second write-gate insulated gate field effect transistors each having its gate electrode coupled to the write enable line and responsive to write enable signals for coupling one and the other of the data lines respectively to the inputs of one and the other of the latches to set the latches in states corresponding to the input data signals on the lines; and first and second read-gate insulated gate field effect transistors each having its gate electrode coupled to the output of a respective one of the latches and responsive to the state of the respective latch for alternatively preparing the coupling or blocking the coupling of the word line to a respective one of the data lines, third and fourth read-gate insulated gate field effect transistors each having its gate electrode coupled to the read line and responsive to read signals for coupling the word line to a respective one of the data lines by way of a respective one of the first and second read-gate transistors, whereby read signals applied to the word line during read cycles are selectively applied to or blocked from the data lines to read out the state of the cell.

Claim 18

The cell set forth in claim 13 further comprising an additional pair of insulated gate field effect transistors each having its gate electrode coupled to a respective one of the data lines and responsive to search signals applied to the respective data line during search/select cycles to selectively apply mismatch signals to the word line by way of a respective one of the first and second read-gate transistors as a function of the logical relationship between the search signals and the cell state.

Claim 19

A functional memory storage cell for selectively storing the four states, 10, 01, 00, 11 of two bits of binary information, said cell having search/select, read and write operational modes, said cell comprising in combination: a pair of terminals adapted for connection to a power supply; first and second stages, each of said stages being associated with a mutually exclusive one of said bits and including first, second, third and fourth N channel insulated gate field gate field effect transistors and first and second P channel insulated gate field effect transistors, each having drain, gate and source electrodes, the source electrodes of said P channel transistors being connected to one of said terminals, the drain electrodes of said first and second P channel transistors being connected to the source electrodes of said first and second N channel transistors, respectively, the drain electrode of said second P channel transistor further being connected to the gate electrodes of said first P channel and N channel transistors and to the source electrode of said third N channel transistor, the drain electrode of said first P channel transistor further being connected to the gate electrodes of said second and fourth N channel transistors and to the gate electrode of said second P channel transistor, means connecting the drain electrodes of said first and second N channel transistors to the other terminal to operate said first P aNd N channel transistors in a complementary manner with respect to each other and said second P and N channel transistors in a complementary manner with respect to each other, whereby said first P channel transistor and said second N channel transistor are in their low impedance states when said second P channel transistor and said first N channel transistor are in their high impedance states and vice versa; first and second bit lines connected to the drain and source electrodes of said third and fourth N channel transistors of said first and second stages, respectively; a write enable line connected to the gate electrodes of said third N channel transistors; a word line connected to the drain electrodes of said fourth N channel transistors; said cell in said search/select operational mode being provided with first and second input signals to said first and second lines, respectively, indicative of a preselected one of the two selectable states 10 and 01, said cell in response to said first and second input signals providing at said word line no output signal whenever the information stored in said cell is in a state that matches the preselected one of said preselectable states and whenever the information stored in said cell is in the state 11, and providing a first output signal whenever the information stored in the cell is in the remaining two other states; said cell in said read operational mode being provided with a third input signal on said word line, said cell, in response to said third input signal, providing at said first and second bit lines signals indicative of the state of said cell; and said cell in said write operational mode being provided with a signal on said write enable line and with input signals on said first and second lines, indicative of a preselected one of said four states for setting the cell in a preselected one of said four states.

Claim 20

A functional memory storage cell for selectively storing the four states, 10, 01, 00, 11 of two bits of binary information, said cell having search/select, read and write operational modes, said cell comprising in combination: a pair of terminals adapted for connection to a power supply; first and second stages, each of said stages being associated with a mutually exclusive one of said bits and including first, second, third and fourth N channel insulated gate field gate field effect transistors and first and second P channel insulated gate field effect transistors, each having drain, gate and source electrodes, the source electrodes of said P channel transistors being connected to one of said terminals, the drain electrodes of said first and second P channel transistors being connected to the source electrodes of said first and second N channel transistors, respectively, the drain electrode of said second P channel transistor further being connected to the gate electrodes of said first P channel and N channel transistors and to the source electrode of said third N channel transistor, the drain electrode of said first P channel transistor further being connected to the gate electrodes of said second and fourth N channel transistors and to the gate electrode of said second P channel transistor, means connecting the drain electrodes of said first and second N channel transistors to the other terminal to operate said first P aNd N channel transistors in a complementary manner with respect to each other and said second P and N channel transistors in a complementary manner with respect to each other, whereby said first P channel transistor and said second N channel transistor are in their low impedance states when said second P channel transistor and said first N channel transistor are in their high impedance states and vice versa; first and second bit lines connected to the drain and source electrodes of said third and fourth N channel transistors of said first and second stages, respectively; a write enable line connected to the gate electrodes of said third N channel transistors; a word line connected to the drain electrodes of said fourth N channel transistors; said cell in said search/select operational mode being provided with first and second input signals to said first and second lines, respectively, indicative of a preselected one of the two selectable states 10 and 01, said cell in response to said first and second input signals providing at said word line no output signal whenever the information stored in said cell is in a state that matches the preselected one of said preselectable states and whenever the information stored in said cell is in the state 11, and providing a first output signal whenever the information stored in the cell is in the remaining two other states; said cell in said read operational mode being provided with a third input signal on said word line, said cell, in response to said third input signal, providing at said first and second bit lines signals indicative of the state of said cell; and said cell in said write operational mode being provided with a signal on said write enable line and with input signals on said first and second lines, indicative of a preselected one of said four states for setting the cell in a preselected one of said four states.

Claim 21

A functional memory storage cell for selectively storing the four states, 10, 01, 00, 11 of two bits of binary information, said cell having search/select, read, and write operational modes, said cell comprising in combination: a pair of terminals adapted for connection to a power supply, first and second stages, each of said stages being associated with a mutually exclusive one of said bits and including first, second, third, fourth, fifth and sixth N channel insulated gate field effect transistors and first and second P channel insulated gate field effect transistors, each having drain, gate and source electrodes, the source electrodes of said P channel transistors and the sixth N channel transistor being connected to one of said terminals, the drain electrodes of said first and second P channel transistors being connected to the source electrodes of said first and second N channel transistors, respectively, the drain electrode of said second P channel transistor further being connected to the gate electrodes of said first P channel and N channel transistors and to the source electrode of said third N channel transistor, the drain electrode of said first P channel transistor further being connected to the gate electrodes of said second and fourth N channel transistors and to the gate electrode of said second P channel transistor, means connecting the drain electrodes of said first and second N channel transistors to the other terminal to operate said first P and N channel transistors in a complementary manner with respect to each other and said second P and N channel transistors in a complementary manner with respect to each other, whereby said first P channel transistor and said second N channel transistor are in their low impedance states when said second P channel transistor and said first N channel transistor are in their high impedance states and vice versa; first and second bit lines connected to the drain, source and gate electrodes Of said third, fifth and sixth N channel transistors of said first and second stages, respectively; the drain electrodes of said fifth and sixth N channel transistors being connected to the source electrode of said fourth N channel transistor; a write enable line connected to the gate electrodes of said third N channel transistors; a word line connected to the drain electrodes of said fourth N channel transistors; a read line connected to the gate electrodes of said fifth N channel transistors; said cell in said search/select operational mode being provided with first and second input signals to said first and second lines, respectively, indicative of a preselected one of the two selectable states 10 and 01, said cell in response to said first and second input signals providing at said word line no output signal whenever the information stored in said cell is in a state that matches the preselected one of said preselectable states and whenever the information stored in said cell is in the state 11, and providing a first output signal whenever the information stored in the cell is in the remaining two other states; said cell in said read operational mode being provided with a third input signal on said word line, said cell, in response to said third input signal, providing at said first and second bit lines signals indicative of the state of said cell; and said cell in said write operational mode being provided with a signal on said write enable line and input signals on said first and second lines, indicative of a preselected one of said four states for setting the cell in a preselected one of said four states.

Claim 22

A functional memory storage cell for selectively storing the four states, 10, 01, 00, 11 of two bits of binary information, said cell having search/select, read, and write operational modes, said cell comprising in combination: a pair of terminals adapted for connection to a power supply, first and second stages, each of said stages being associated with a mutually exclusive one of said bits and including first, second, third, fourth, fifth and sixth N channel insulated gate field effect transistors and first and second P channel insulated gate field effect transistors, each having drain, gate and source electrodes, the source electrodes of said P channel transistors and the sixth N channel transistor being connected to one of said terminals, the drain electrodes of said first and second P channel transistors being connected to the source electrodes of said first and second N channel transistors, respectively, the drain electrode of said second P channel transistor further being connected to the gate electrodes of said first P channel and N channel transistors and to the source electrode of said third N channel transistor, the drain electrode of said first P channel transistor further being connected to the gate electrodes of said second and fourth N channel transistors and to the gate electrode of said second P channel transistor, means connecting the drain electrodes of said first and second N channel transistors to the other terminal to operate said first P and N channel transistors in a complementary manner with respect to each other and said second P and N channel transistors in a complementary manner with respect to each other, whereby said first P channel transistor and said second N channel transistor are in their low impedance states when said second P channel transistor and said first N channel transistor are in their high impedance states and vice versa; first and second bit lines connected to the drain, source and gate electrodes Of said third, fifth and sixth N channel transistors of said first and second stages, respectively; the drain electrodes of said fifth and sixth N channel transistors being connected to the source electrode of said fourth N channel transistor; a write enable line connected to the gate electrodes of said third N channel transistors; a word line connected to the drain electrodes of said fourth N channel transistors; a read line connected to the gate electrodes of said fifth N channel transistors; said cell in said search/select operational mode being provided with first and second input signals to said first and second lines, respectively, indicative of a preselected one of the two selectable states 10 and 01, said cell in response to said first and second input signals providing at said word line no output signal whenever the information stored in said cell is in a state that matches the preselected one of said preselectable states and whenever the information stored in said cell is in the state 11, and providing a first output signal whenever the information stored in the cell is in the remaining two other states; said cell in said read operational mode being provided with a third input signal on said word line, said cell, in response to said third input signal, providing at said first and second bit lines signals indicative of the state of said cell; and said cell in said write operational mode being provided with a signal on said write enable line and input signals on said first and second lines, indicative of a preselected one of said four states for setting the cell in a preselected one of said four states.