Method and apparatus for reordering data

Claim 2

Apparatus for buffering and digits-reversed scrambling an input sequence of ordered signals to generate sets of N output signals comprising A. a memory having N storage locations, B input addressing means for generating alternate patterns of straight sequential address input signals and scrambled-withinquadrant address input signals, C output addressing means for generating patterns of signals representing output addresses having digits of greatest significance varying for each set of R consecutive addresses, where R is an integer factor of N, D means responsive to said input address signals for causing said input sequence of ordered signals to be stored at corresponding locations in said memory, and E means responsive to said output address signals for reading out signals stored in said memory, thereby deriving said output signals.

Claim 3

a modulo-N/R counter for generating a plurality of first count signals representative of a count of said first clock signals, R and N/R being positive integers,

Claim 4

a modulo-N/R counter for generating a plurality of first count signals representative of a count of said first clock signals, R and N/R being positive integers,

Claim 5

Apparatus according to claim 1 wherein said input addressing means comprises

Claim 6

a modulo-N counter for generating a plurality of second count signals representative of a count of said second clock signals,

Claim 7

a modulo-N counter for generating a plurality of second count signals representative of a count of said second clock signals,

Claim 8

a modulo-N counter for generating a plurality of second count signals representative of a count of said second clock signals,

Claim 9

a modulo-N counter for generating a plurality of second count signals representative of a count of said second clock signals,

Claim 10

a modulo-R counter for generating first output address signals representative of the number of transitions of said modulo-N counter from its maximum count to its minimum count, and

Claim 11

a modulo-R counter for generating first output address signals representative of the number of transitions of said modulo-N counter from its maximum count to its minimum count, and

Claim 12

a modulo-R counter for generating first output address signals representative of the number of transitions of said modulo-N counter from its maximum count to its minimum count, and

Claim 13

a modulo-R counter for generating first output address signals representative of the number of transitions of said modulo-N counter from its maximum count to its minimum count, and

Claim 14

Apparatus according to claim 2 wherein R represents the redundancy for said sets of N output signals and wherein said first source of clock signals comprises means for generating clock signals at the rate of N/R per second.

Claim 15

a modulo-R counter for generating a set of first address signals representative of the number of transitions of said modulo-N/R counter from its maximum count to its minimum count, and

Claim 16

a modulo-R counter for generating a set of first address signals representative of the number of transitions of said modulo-N/R counter from its maximum count to its minimum count, and

Claim 17

means responsive to said first address signals for selectively reversing the significance of selected ones of said first count signals, thereby to generate second address signals.

Claim 18

means responsive to said first address signals for selectively reversing the significance of selected ones of said first count signals, thereby to generate second address signals.

Claim 19

means responsive to said first output address signals for selectively reversing the significance of selected ones of said second count signals, thereby to generate second output address signals.

Claim 20

means responsive to said first output address signals for selectively reversing the significance of selected ones of said second count signals, thereby to generate second output address signals.

Claim 21

means responsive to said first output address signals for selectively reversing the significance of selected ones of said second count signals, thereby to generate second output address signals.

Claim 22

means responsive to said first output address signals for selectively reversing the significance of selected ones of said second count signals, thereby to generate second output address signals.

Claim 23

Apparatus according to claim 1 wherein said output addressing means comprises

Claim 24

Apparatus for generating a sequence of input addresses for a memory having N locations comprising A. a source of clock signals, B. a modulo-N/R counter for generating first count signals representative of a count of said clock signals, R and N/R being Positive integers, C. a modulo-R counter for generating first address signals representative of the number of transitions of said modulo-N/R counter from maximum count to minimum count, R and N/R being positive integers, and D. means responsive to said first address signals for selectively reversing the significance of selected ones of said first count signals, thereby to generate second address signals.

Claim 25

Apparatus for generating a sequence of input addresses for a memory having N locations comprising A. a source of clock signals, B. a modulo-N/R counter for generating first count signals representative of a count of said clock signals, R and N/R being Positive integers, C. a modulo-R counter for generating first address signals representative of the number of transitions of said modulo-N/R counter from maximum count to minimum count, R and N/R being positive integers, and D. means responsive to said first address signals for selectively reversing the significance of selected ones of said first count signals, thereby to generate second address signals.

Claim 26

Apparatus according to claim 5 wherein each of said counters is a binary counter and said means responsive to said first address signals comprises means for reversing the significance of the bits of said modulo-N/R counter.

Claim 27

Apparatus for generating a sequence of output address signals for a memory having N locations comprising

Claim 28

Apparatus for generating a sequence of output address signals for a memory having N locations comprising

Claim 29

Apparatus according to claim 7 wherein each of said counters is a binary counter, and said means responsive to said first output address signals comprises a control means for selectively reversing the significance of the signals representing the log2(N/R) most significant bits of said modulo-N counter.

Claim 30

Apparatus according to claim 8 wherein said control means comprises an R-bit adder for forming the sum of the signals representing the R least significant bits of said modulo-N counter and the contents of said modulo-R counter, said adder also comprising means for generating an overflow signal, and second control means responsive to said overflow signal for reversing the significance of said log2(N/R) most significant bits of said modulo-N counter.

Claim 31

Apparatus according to claim 9 wherein said second control means also comprises means responsive to said first output address signals for reversing the significance of said log2(N/R) bits.

Claim 32

Apparatus according to claim 10 for combining said first and second output address signals, thereby to form composite output address signals.

Claim 33

The machine method for generating sets of N output signal sequences each of which is a digits-reversed reordered version of a corresponding input signal sequence comprising the steps of A. generating a sequence of binary input address signals, said address signals indicating alternate R-address subsequences of addresses having a straight-sequential ordering and scrambled-within-quadrant ordering, B. storing each of said sequences in a memory having N locations, the locations for storing said sequences being determined by said sequence of input address signals, C. generating a sequence of binary output address signals which indicate addresses for which the N/R digits of greatest significance vary for sets of R consecutive addresses, and D. reading sets of N signals from locations in said memory in accordance with said sequence of output addresses.

Claim 34

The machine method for generating sets of N output signal sequences each of which is a digits-reversed reordered version of a corresponding input signal sequence comprising the steps of A. generating a sequence of binary input address signals, said address signals indicating alternate R-address subsequences of addresses having a straight-sequential ordering and scrambled-within-quadrant ordering, B. storing each of said sequences in a memory having N locations, the locations for storing said sequences being determined by said sequence of input address signals, C. generating a sequence of binary output address signals which indicate addresses for which the N/R digits of greatest significance vary for sets of R consecutive addresses, and D. reading sets of N signals from locations in said memory in accordance with said sequence of output addresses.

Claim 35

The method of claim 12 wherein said step of generating said sequence of binary input addresses comprises (1) generating a sequence of clock signals at the desired input signal rate, (2) modulo-N/R counting said clock signals, thereby generating first count signals, (3) modulo-R counting the number of cycles occurring in said modulo-N/R counting of said clock signals, thereby generating first input address signals, and (4) selectively bit-reversing said first count signals in response to an indication of the number of cycles of said modulo-R counter, thEreby generating second input address signals.