Phase locked frequency modulation demodulator circuit including colpitts transistor and feedback transistor

Claim 2

A phase locked frequency modulation demodulator circuit comprising: a transistor having an emitter electrode, a collector electrode, and a base electrode; first, second, and third terminals to which circuit operating potentials are applied, said first terminal being coupled to said emitter electrode, said third terminal being coupled to said collector electrode; means for providing an inductance between said base electrode and said second terminal and for providing a capacitance between said emitter electrode and said third terminal, whereby circuit oscillation may be achieved; means for applying a frequency modulated carrier signal to said emitter electrode; feedback means coupled between said collector and emitter electrodes for providing an effective inductance in parallel with said capacitance and for varying said effective inductance in accordance with an error signal indicative of the frequency difference between said frequency modulated signal and a signal at the instantaneous oscillation frequency of the circuit to vary the instantaneous oscillation frequency of the circuit accordingly, said error signal containing an amplitude varying component indicative of the modulation on said frequency modulated carrier signal; and means coupled to said collector electrode for removing the carrier frequency component from said error signal.

Claim 3

A phase locked frequency modulation demodulator circuit according to claim 1 wherein the last named means includes means coupled to said collector electrode for amplifying said error signal and a low-pass filter coupled to said amplifying means.

Claim 4

A phase locked frequency modulation demodulator circuit comprising: a first transistor having an emitter electrode, a collector electrode, and a base electrode; first, second, third terminals to which circuit operating potentials are applied, said first terminal being coupled to said emitter electrode, said third terminal being coupled to said collector electrode; means for providing an inductance between said base electrode and said second terminal and for providing a capacitance between said emitter electrode and said third terminal, whereby circuit oscillation may be achieved; means for applying a fRequency modulated carrier signal to said emitter electrode; means including a second transistor for varying the effective capacitance in parallel with said inductance in accordance with an error signal indicative of the frequency difference between said frequency modulated signal and a signal at the instantaneous oscillation frequency of the circuit to vary the instantaneous oscillation frequency of the circuit accordingly, said error signal containing an amplitude varying component indicative of the modulation on said frequency modulated carrier signal; means coupled to the collector electrode of said first transistor for removing the carrier frequency component from said error signal; said second transistor having a base electrode coupled to the collector electrode of said first transistor and having respective emitter and collector electrodes coupled to said third and first terminals, respectively; and said means including said second transistor further including a feedback impedance coupled between the collector electrode of said second transistor and the emitter electrode of said first transistor.

Claim 5

A phase locked frequency modulation demodulator circuit comprising: a first transistor having an emitter electrode, a collector electrode, and a base electrode; first, second, third terminals to which circuit operating potentials are applied, said first terminal being coupled to said emitter electrode, said third terminal being coupled to said collector electrode; means for providing an inductance between said base electrode and said second terminal and for providing a capacitance between said emitter electrode and said third terminal, whereby circuit oscillation may be achieved; means for applying a fRequency modulated carrier signal to said emitter electrode; means including a second transistor for varying the effective capacitance in parallel with said inductance in accordance with an error signal indicative of the frequency difference between said frequency modulated signal and a signal at the instantaneous oscillation frequency of the circuit to vary the instantaneous oscillation frequency of the circuit accordingly, said error signal containing an amplitude varying component indicative of the modulation on said frequency modulated carrier signal; means coupled to the collector electrode of said first transistor for removing the carrier frequency component from said error signal; said second transistor having a base electrode coupled to the collector electrode of said first transistor and having respective emitter and collector electrodes coupled to said third and first terminals, respectively; and said means including said second transistor further including a feedback impedance coupled between the collector electrode of said second transistor and the emitter electrode of said first transistor.

Claim 6

A phase locked frequency modulation demodulator circuit according to claim 3 wherein said means including said second transistor further includes means coupled to the collector electrode of said first transistor for amplifying said error signal and a low-pass filter coupled to said amplifying means.

Claim 7

A phase locked frequency modulation demodulator circuit according to claim 3 wherein said frequency modulated carrier signal applying means includes a third transistor having a base electrode adapted to receive a frequency modulated input signal, a collector electrode resistively coupled to the emitter electrode of said first transistor, and an emitter electrode coupled to said third terminal.

Claim 8

A phase locked frequency modulation demodulator circuit according to claim 1 wherein said feedback means includes a second transistor having a base electrode coupled to said collector electrode, a collector electrode coupled to said emitter electrode and to said first terminal, and an emitter electrode coupled to said third terminal.

Claim 9

A phase locked frequency modulation demodulator circuit according to claim 3 wherein said second transistor is of a conductivity type complementary to that of said first transistor.

Claim 10

A phase locked frequency modulation demodulator circuit according to claim 3 wherein a first load impedance is coupled between said first terminal and the emitter electrode of said first transistor, a second load impedance is coupled between said first terminal and the collector electrode of said second transistor, and a third load impedance is coupled between said third terminal and the collector electrode of said first transistor.

Claim 11

A phase locked frequency modulation demodulator circuit comprising: a transistor having an emitter electrode, a collector electrode, and a base electrode; first, second, and third terminals to which circuit operating potentials are applied, said first terminal being coupled to said emitter electrode, said third terminal being coupled to said collector electrode; means for providing an inductance between said base electrode and said second terminal and for providing a capacitance between said emitter electrode and said third terminal, whereby circuit oscillation may be achieved; means for applying a frequency modulated carrier signal to the emitter-collector path of said transistor; feedback means coupled between said collector and emitter electrodes for providing an effective inductance in parallel with said capacitance and for varying said effective inductance in accordance with an error signal indicative of the frequency difference between said frequency modulated signal and a signal at the instantaneous oscillation frequency of the circuit to vary the instantaneous oscillation frequency of the circuit accordingly, said error signal containing an amplitude varying component indicative of the modulation on said frequenCy modulated carrier signal; and means coupled to said collector electrode for removing the carrier frequency component from said error signal.

Claim 12

A phase locked frequency modulation demodulator circuit comprising: a transistor having an emitter electrode, a collector electrode, and a base electrode; first, second, and third terminals to which circuit operating potentials are applied, said first terminal being coupled to said emitter electrode, said third terminal being coupled to said collector electrode; means for providing an inductance between said base electrode and said second terminal and for providing a capacitance between said emitter electrode and said third terminal, whereby circuit oscillation may be achieved; means for applying a frequency modulated carrier signal to the emitter-collector path of said transistor; feedback means coupled between said collector and emitter electrodes for providing an effective inductance in parallel with said capacitance and for varying said effective inductance in accordance with an error signal indicative of the frequency difference between said frequency modulated signal and a signal at the instantaneous oscillation frequency of the circuit to vary the instantaneous oscillation frequency of the circuit accordingly, said error signal containing an amplitude varying component indicative of the modulation on said frequenCy modulated carrier signal; and means coupled to said collector electrode for removing the carrier frequency component from said error signal.

Claim 13

A phase locked frequency modulation demodulator circuit according to claim 9 wherein said feedback means includes a second transistor having a base electrode coupled to said collector electrode, a collector electrode coupled to said emitter electrode and to said first terminal, and an emitter electrode coupled to said third terminal.

Claim 14

A phase locked frequency modulation demodulator circuit according to claim 10 wherein a first load impedance is coupled between said first terminal and the emitter electrode of said first transistor, a second load impedance is coupled between said first terminal and the collector electrode of said second transistor, and a third load impedance is coupled between said third terminal and the collector electrode of said first transistor.