Patent US3739172A successfully refreshed from Google Patents.
US3739172A
Expired / Lapsed
US
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Circuit for improving data in pulse detection systems
Assignee: Western Atlas International Inc
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Filing: 1971-05-24
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Granted: 1973-06-12
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Expires: 1991-05-24
Abstract
Abstract The amplified pulses from a radioactivity detector are coupled through a delay line to a linear gate. The amplified pulses from the detector are also connected to a discriminator. The output of the discriminator is AND gated in a logical gate with a clock pulse which is synchronized with a high energy neutron source. The AND gate triggers a single shot multivibrator which in turn triggers the linear gate. The delay line allows for the time required for the detector pulse to rise to the discriminator threshold and for the propagation delay in the logic circuitry. The linear gate opens before the arrival of the detector pulse and closes after it passes through. In this embodiment, any detector pulse having the necessary discriminator level occuring within the clock pulse interval passes through the linear gate as a full width pulse. In an alternative embodiment, a J-K flip-flop circuit is triggered by the trailing edge of the single shot multivibrator to disable the AND gate, thus causing the linear gate to pass only the first detected pulse having the necessary discriminator level.
Inventors
- 👤 R Culver
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 06:38
CPC Classifications
G; G01; G01V; G01V5/00; G01V5/04; G01V5/08; G01V5/10; G01V5/101; G01V5/102
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
64 words
In a radioactivity well logging system having a pulsed neutron source and a radioactivity detector system having electrical pulses at its output wherein electrical pulses tend to pile up within the system, the improvement comprising means to selectively gate only a single electrical pulse from the output of said radioactivity detector system indicative of detected radiation following the commencement of each neutron source pulse.
Claim 2
Dependent Claim
64 words
In a radioactivity well logging system having a pulsed neutron source and a radioactivity detector system having electrical pulses at its output wherein electrical pulses tend to pile up within the system, the improvement comprising means to selectively gate only a single electrical pulse from the output of said radioactivity detector system indicative of detected radiation following the commencement of each neutron source pulse.
Claim 3
Dependent Claim
24 words
In the system according to claim 1, said selective gating means being further characterized as being synchronized with the pulsing of said neutron source.
Claim 4
Dependent Claim
27 words
In the system according to claim 2, said selective gating means being further characterized as including means to discriminately gate only those pulses having a predetermined characteristic.
Claim 5
Dependent Claim
31 words
In the system according to claim 3, wherein said predetermined characteristic is functionally related to the energy level of gamma rays of interest emanating from the formations surrounding the well bore.
Claim 6
Dependent Claim
37 words
In the system according to claim 2, said selective gating means being further characterized as including means to gate only the first such electrical pulse following a preselected event associated with the pulsing of said neutron source.
Claim 7
Dependent Claim
135 words
In an electrical circuit in which electrical pulses are cyclically associated with a synchronized event, the improvement comprising: clock means for producing a series of synchronizing gate pulses; an input terminal for receiving electrical pulses associated with said synchronizing gate pulses; delay means connected to said input terminal; a first electrical gate connected to the output of said delay means; a second electrical AND gate having two gate inputs, the first of said gate inputs being connected to said clock means and the second of said gate inputs being connected to said input terminal; a single shot multivibrator connected to the output of said AND gate, the output of said multivibrator being connected to said first electrical gate for triggering said first gate; and an output terminal connected to the output of said first gate.
Claim 8
Dependent Claim
135 words
In an electrical circuit in which electrical pulses are cyclically associated with a synchronized event, the improvement comprising: clock means for producing a series of synchronizing gate pulses; an input terminal for receiving electrical pulses associated with said synchronizing gate pulses; delay means connected to said input terminal; a first electrical gate connected to the output of said delay means; a second electrical AND gate having two gate inputs, the first of said gate inputs being connected to said clock means and the second of said gate inputs being connected to said input terminal; a single shot multivibrator connected to the output of said AND gate, the output of said multivibrator being connected to said first electrical gate for triggering said first gate; and an output terminal connected to the output of said first gate.
Claim 9
Dependent Claim
26 words
In the circuit according to claim 6, being further characterized as including discriminator means between said input terminal and the second of said AND gate inputs.
Claim 10
Dependent Claim
16 words
In the circuit according to claim 7, wherein said first electrical gate is a linear gate.
Claim 11
Dependent Claim
215 words
In an electrical circuit in which electrical pulses are cyclically associated with a synchronized event, the improvement comprising: clock means for producing a series of synchronizing gate pulses; an input terminal for receiving elecTrical pulses associated with said synchronizing gate pulses; delay means connected to said input terminal; a first electrical gate connected to the output of said delay means; a J-K flip-flop circuit having a first input steering terminal, a clearing input terminal and a clock input terminal and providing an output signal at an output terminal of said flip-flop circuit, said clearing input terminal being connected to said clock means; a second electrical AND gate having three inputs, the first of said gate inputs being connected to said clock means and the second of said gate inputs being connected to said input terminal; a single shot multivibrator connected to the output of said AND gate, the output of said multivibrator being connected to said first electrical gate for triggering said first gate and also being connected to the clock input terminal of said J-K flip-flop circuit, said input steering terminal being connected to said output terminal of said J-K flip-flop circuit and to the third gate input of said AND gate; and an output terminal connected to the output of said first gate.
Claim 12
Dependent Claim
215 words
In an electrical circuit in which electrical pulses are cyclically associated with a synchronized event, the improvement comprising: clock means for producing a series of synchronizing gate pulses; an input terminal for receiving elecTrical pulses associated with said synchronizing gate pulses; delay means connected to said input terminal; a first electrical gate connected to the output of said delay means; a J-K flip-flop circuit having a first input steering terminal, a clearing input terminal and a clock input terminal and providing an output signal at an output terminal of said flip-flop circuit, said clearing input terminal being connected to said clock means; a second electrical AND gate having three inputs, the first of said gate inputs being connected to said clock means and the second of said gate inputs being connected to said input terminal; a single shot multivibrator connected to the output of said AND gate, the output of said multivibrator being connected to said first electrical gate for triggering said first gate and also being connected to the clock input terminal of said J-K flip-flop circuit, said input steering terminal being connected to said output terminal of said J-K flip-flop circuit and to the third gate input of said AND gate; and an output terminal connected to the output of said first gate.
Claim 13
Dependent Claim
26 words
In the circuit according to claim 9, being further characterized as including discriminator means between said input terminal and the second of said AND gate inputs.
Claim 14
Dependent Claim
16 words
In the circuit according to claim 10, wherein said first electrical gate is a linear gate.
Claim 15
Dependent Claim
195 words
In an electrical circuit in which electrical pulses are cyclically associated with a synchronized event, the improvement comprising: clock means for producing a series of synchronizing gate pulses; an input terminal for receiving electrical pulses associated with said synchronizing gate pulses; delay means connected to said input terminal; a first electrical gate connected to the output of said delay means; a second electrical AND gate having three gate inputs, the first of said gate inputs being connected to said clock means and the second of said gate inputs being connected to said input terminal; a single shot multivibrator connected to the output of said AND gate, the output of said multivibrator being connected to said first electrical gate for triggering said first gate; bistable circuit means responsive to said clock means and to the output of said single shot multivibrator, the output of said circuit means being connected to the third input of said AND gate, whereby said bistable means are in one stable condition in response to said clock means and in another stable position in response to said single shot multivibrator; and an output terminal connected to the output of said first gate.
Claim 16
Dependent Claim
195 words
In an electrical circuit in which electrical pulses are cyclically associated with a synchronized event, the improvement comprising: clock means for producing a series of synchronizing gate pulses; an input terminal for receiving electrical pulses associated with said synchronizing gate pulses; delay means connected to said input terminal; a first electrical gate connected to the output of said delay means; a second electrical AND gate having three gate inputs, the first of said gate inputs being connected to said clock means and the second of said gate inputs being connected to said input terminal; a single shot multivibrator connected to the output of said AND gate, the output of said multivibrator being connected to said first electrical gate for triggering said first gate; bistable circuit means responsive to said clock means and to the output of said single shot multivibrator, the output of said circuit means being connected to the third input of said AND gate, whereby said bistable means are in one stable condition in response to said clock means and in another stable position in response to said single shot multivibrator; and an output terminal connected to the output of said first gate.
Claim 17
Dependent Claim
26 words
In the circuit according to claim 12, being further characterized as including discriminator means between said input terminal and the second of said AND gate inputs.
Claim 18
Dependent Claim
16 words
In the circuit according to claim 13, wherein said first electrical gate is a linear gate.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-06-11 | 1976-12-11 | 1977-06-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-06-11 | 1980-12-11 | 1981-06-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-06-11 | 1984-12-11 | 1985-06-12 | $7700.00 | Window Closed / Lapsed |