Charge circuit for field effect transistor logic gate

Claim 2

A field effect transistor logic gate comprising: a field effect transistor having a base region, source and drain means forming junctions with said base region, gate means for controlling current flow between said source and drain means, and an electrode connected to said base region; an output terminal; a logic network having two terminals; means connecting said field effect transistor in electrical series between said output terminal and one terminal of said logic network; potential means applied to said electrode and poled to provide current flow paths from said electrode through respective ones of said junctions to said one terminal of said logic network and to said output terminal during a first operating interval; means connected to apply input signals having first and second logic levels to said logic network, said logic network assuming a conductive condition between said two terminals in response to an input signal of said first level and assuming a blocked condition in response to an input signal of said second level; means connected to said gate means during a second operating interval, for turning on said field effect transistor during said second operating interval to connect said output terminal to said logic network, whereby an output signal is derived dependent upon the condition of the logic network.

Claim 3

A logic gate as in claim 1 and further including capacitance means associated with said one terminal and said output terminal, said capacitance means being precharged by said current flow during said first operating interval and being conditionally discharged through the series path of said field effect transistor and said logic network during said second operating interval.

Claim 4

A field effect transistor logic gate having an operation cycle determined by multiple phase clock signals wherein said cycle includes a precharge interval followed by an input evaluation interval, said logic gate comprising: a first field effect transistor having a base region, source and drain means forming diode junctions with said base region, gate means for controlling current flow between said source and drain means, and a precharge electrode connected to said base region; an output terminal; first capacitance means connected to said output terminal; a logic network having two terminals and including at least a second field effect transistor having source, drain, and gate electrodes with its source-to-drain path connected between the two logic network terminals; means connecting said first field effect transistor in electrical series between said output terminal and one terminal of said logic network; second capacitance means connected to said one terminal of said logic network; first clock signal means connected to said precharge electrode during said precharge interval and poled to provide current flow paths from said electrode through respective ones of said diode junctions to said one Terminal of said logic network and to said output terminal to precharge said first and second capacitance means during said precharge interval; means connected to the gate electrode of said second field effect transistor for applying input signals having first and second logic levels, said logic network assuming a conductive condition between said terminals in response to an input signal of said first level and assuming a blocked condition in response to an input signal of said second level; and second clock signal means connected to said gate means of said first field effect transistor at least during said input evaluation interval for turning on said first field effect transistor during said input evaluation interval to connect said output terminal to said logic network, whereby said first capacitance means is conditionally discharged through said first field effect transistor and said logic network to derive an output signal dependent upon the condition of the logic network.

Claim 5

A field effect transistor logic gate having an operation cycle determined by multiple phase clock signals wherein said cycle includes a precharge interval followed by an input evaluation interval, said logic gate comprising: a first field effect transistor having a base region, source and drain means forming diode junctions with said base region, gate means for controlling current flow between said source and drain means, and a precharge electrode connected to said base region; an output terminal; first capacitance means connected to said output terminal; a logic network having two terminals and including at least a second field effect transistor having source, drain, and gate electrodes with its source-to-drain path connected between the two logic network terminals; means connecting said first field effect transistor in electrical series between said output terminal and one terminal of said logic network; second capacitance means connected to said one terminal of said logic network; first clock signal means connected to said precharge electrode during said precharge interval and poled to provide current flow paths from said electrode through respective ones of said diode junctions to said one Terminal of said logic network and to said output terminal to precharge said first and second capacitance means during said precharge interval; means connected to the gate electrode of said second field effect transistor for applying input signals having first and second logic levels, said logic network assuming a conductive condition between said terminals in response to an input signal of said first level and assuming a blocked condition in response to an input signal of said second level; and second clock signal means connected to said gate means of said first field effect transistor at least during said input evaluation interval for turning on said first field effect transistor during said input evaluation interval to connect said output terminal to said logic network, whereby said first capacitance means is conditionally discharged through said first field effect transistor and said logic network to derive an output signal dependent upon the condition of the logic network.

Claim 6

The logic gate as in claim 3 wherein said second clock signal means is connected to said gate means during both said precharge interval and said input evaluation interval.

Claim 7

The logic gate as in claim 4 wherein said first clock signal means is further connected to the second terminal of said logic network during said precharge interval to prevent premature power dissipation through said logic network prior to said input evaluation interval.