Abstract An insulated-gate field effect transistor is described which comprises a semiconductor substrate in which an insulated gate field effect transistor, and first and second regions having impurities at a high concentrations are formed. The first region is of the opposite conductivity type as that of the substrate, while the second region is of the same conductivity type as that of the substrate. The second region is in contact with one end of the first region, and the second region and/or the substrate is grounded. The end of the first region in contact with the second region is connected to the gate electrode of the insulated gate field effect transistor, and the other end of the first region is connected to the input electrode.
An insulated gate field effect transistor with means for protecting against excessive gate voltage comprising a semiconductor substrate having a first conductivity type; an insulated gate field effect transistor formed in said substrate having source and drain regions of a second conductivity type opposite to said first conductivity type, source and drain electrodes respectively connected to said source and drain regions, and a gate electrode formed on an insulator film lying on said substrate in the region between said source and drain electrodes; a generally elongated first resistance region formed on said substrate separately from said transistor, having a high impurity concentration of said second conductivity type, an input terminal connected to one end of said resistance region, and an output terminal connected to the other end of said resistance region, a first P-N junction being formed at said one end between said resistance region and said substrate; a second region formed on said substrate in contact with said other end of said first region, a second P-N junction being formed between said second region and said resistance region at said other end, said second region having a relatively high impurity concentration of said first conductivity type as compared to said substrate, means for connecting said output terminal to said gate electrode, the breakdown voltage of said second P-N junction being lower than that of said first P-N junction, whereby the application of an excessive voltage to said input terminal causes a breakdown of said second P-N junction, such that a voltage reduced by the amount of the voltage drop across said first resistance region is developed at said output terminal, a third region of one of said first and second conductivity types formed in said substrate and having a high impurity concentration disposed adjacent to said other end of said first region, and a wiring layer formed on said substrate for grounding said third region.
Claim 2
Dependent Claim
316 words
An insulated gate field effect transistor with means for protecting against excessive gate voltage comprising a semiconductor substrate having a first conductivity type; an insulated gate field effect transistor formed in said substrate having source and drain regions of a second conductivity type opposite to said first conductivity type, source and drain electrodes respectively connected to said source and drain regions, and a gate electrode formed on an insulator film lying on said substrate in the region between said source and drain electrodes; a generally elongated first resistance region formed on said substrate separately from said transistor, having a high impurity concentration of said second conductivity type, an input terminal connected to one end of said resistance region, and an output terminal connected to the other end of said resistance region, a first P-N junction being formed at said one end between said resistance region and said substrate; a second region formed on said substrate in contact with said other end of said first region, a second P-N junction being formed between said second region and said resistance region at said other end, said second region having a relatively high impurity concentration of said first conductivity type as compared to said substrate, means for connecting said output terminal to said gate electrode, the breakdown voltage of said second P-N junction being lower than that of said first P-N junction, whereby the application of an excessive voltage to said input terminal causes a breakdown of said second P-N junction, such that a voltage reduced by the amount of the voltage drop across said first resistance region is developed at said output terminal, a third region of one of said first and second conductivity types formed in said substrate and having a high impurity concentration disposed adjacent to said other end of said first region, and a wiring layer formed on said substrate for grounding said third region.
Claim 3
Dependent Claim
25 words
The semiconductor device as claimed in claim 1, wherein said third region is of said second conductivity type and is formed in said second region.
Claim 4
Dependent Claim
18 words
The semiconductor device as claimed in claim 1, wherein said third region is of said first conductivity type.