Program interrupt facilities in data processing systems

Claim 2

A data processing system comprising in combination: a plurality of processor units; a plurality of peripheral units; a memory having addressable locations for storing data words and program instruction words and including a system interrupt storage area for the storage of a plurality of interrupt demand indicating bits, there being one such bit in said storage area allocated to each processor unit and each peripheral unit on a mutually exclusive basis, and means for setting said demand indicating bit when a processor or a peripheral unit is required to generate a system interrupt; a communication medium providing intercommunication between said memory and said processor and peripheral units; each said processor unit being provided with interrupt apparatus including an interrupt interrogate pulse generator for periodically producing an interrupt interrogate pulse to activate (i) nine means for inhibiting the operations currently being performed by the associated processor unit, (ii) nine means for addressing said memory at said storage area and interrogating the state of the bits therein and (iii) nine means for detecting a set interrupt indicating bit, said interrupt apparatus further including interrupt acceptance means activated by the detection of a set interrupt demand indicating bit and operable to control the processor unit in the execution of interrupt handling operations.

Claim 3

A data processing system according to claim 1 wherein said memory also includes a plurality of dedicated local storage Areas each of which is particular to one of said processor units, each dedicated local storage area including storage for an interrupt accept bit mask, defining the interrupt demands which are currently to be acceptable to the particular processor unit to which the local storage area is dedicated, and said interrupt apparatus includes comparing means for comparing the states of said interrupt demand indicating bits with the states of the pertinent interrupt accept bit mask to ascertain if any of the interrupt demand indicating bits currently acceptable to said particular processor unit are set before operating said interrupt acceptance means.

Claim 4

A data processing system according to claim 2 wherein said interrupt apparatus includes an interrupt accept word computing means which computes a code indicative of one of said acceptance interrupt demand indicating bits.

Claim 5

A data processing system according to claim 3 wherein said interrupt apparatus includes set bit reset means responsive to the code in said interrupt accept register and operable to reset the set bit in said storage area corresponding to said code.

Claim 6

A data processing system comprising in combination: a plurality of processor units; a plurality of peripheral units; a memory having a plurality of storage modules each including addressable locations for storing data and program instructions and one of said storage modules includes a system interrupt storage area for the storage of a plurality of interrupt demand indicating bits, there being one such bit in said storage area allocated on a mutually exclusive basis to each processor unit and each peripheral unit, and means for setting said demand indicating bit when a processor or a peripheral unit is required to generate a system interrupt; a communication medium providing intercommunication between said memory and said processor and peripheral units; each said processor unit being provided with interrupt apparatus including an interrupt interrogate pulse generator for periodically producing an interrupt interrogate pulse to activate, (i) nine first means for inhibiting the operations currently being performed by the associated processor unit, (ii) nine second means for addressing said memory at said storage area and reading the state of the bits therein, (iii) nine third means for detecting a set interrupt indicating bit, (iv) nine fourth means for registering a code indicative of a selected one of said set interrupt indicating bits and (v) nine fifth means for resetting said selected one of said set interrupt indicating bits; and memory module locking means for preventing access to said one of said storage modules, during the period of operation of said second, third and fifth means, by any other processor or peripheral unit of the system.

Claim 7

A data processing system comprising in combination: a plurality of processor units; a plurality of peripheral units; a memory having a plurality of storage modules each including addressable locations for storing data and program instructions and one of said storage modules includes a system interrupt storage area for the storage of a plurality of interrupt demand indicating bits, there being one such bit in said storage area allocated on a mutually exclusive basis to each processor unit and each peripheral unit, and means for setting said demand indicating bit when a processor or a peripheral unit is required to generate a system interrupt; a communication medium providing intercommunication between said memory and said processor and peripheral units; each said processor unit being provided with interrupt apparatus including an interrupt interrogate pulse generator for periodically producing an interrupt interrogate pulse to activate, (i) nine first means for inhibiting the operations currently being performed by the associated processor unit, (ii) nine second means for addressing said memory at said storage area and reading the state of the bits therein, (iii) nine third means for detecting a set interrupt indicating bit, (iv) nine fourth means for registering a code indicative of a selected one of said set interrupt indicating bits and (v) nine fifth means for resetting said selected one of said set interrupt indicating bits; and memory module locking means for preventing access to said one of said storage modules, during the period of operation of said second, third and fifth means, by any other processor or peripheral unit of the system.

Claim 8

A data processing system according to claim 5 wherein each processor unit is provided with a pair of time counters, a first of said counters being arranged to define information indicative of the length of time spent on processing the current operations while a second of said counters is arranged to define information indicative of the length of time elapsed since a particular control operation was performed and each said processor unit includes first and second internal interrupt demand indicating devices which are switched to the demand state when said first and second registers respectively reach a pre-determined state of count and said interrupt pulse generator is activated immediately by means responsive to said internal interrupt demand indicating devices.

Claim 9

A data processing system according to claim 6 wherein said memory also includes a plurality of dedicated local storage areas each of which is particular to one of said processor units, each dedicated local storage area including storage for an interrupt accept bit mask, defining the interrupt demands which are currently to be acceptable to the particular processor unit to which the local storage area is dedicated and said seconD means reads the states of all said interrupt demand indicating bits from said storage area into an internal register in said processor unit together with the states of said first and second internal interrupt demand indicating devices and a mask register is provided in each processor unit into which the appropriate interrupt bit mask is read and comparison means are provided in said processor unit to merge the information in said internal register with the information in said mask register.

Claim 10

A data processing system according to claim 7 wherein said processor units include means for correlating the result of the merging of the information in said internal register with the information in said mask register and the result of the correlation is written into an interrupt accept register.