Set-reset flip-flop

Claim 2

In combination with first and second storage devices each having an input and an output and having coupling means for selectively transferring the output of the first device to the input of the second device, a set-reset circuit comprising: first and second points of operating potential; a first transistor directly connected between said first point and said input of said first device; a second transistor directly connected between said second point and said input of said first device; means for selectively enabling one of said first and second transistors for switching said first device to either a first or a second storage condition, respectively; and means for enabling said coupling means concurrently with the enabling of said first or second transistors for transferring the ouput of said first device to the input of said second device.

Claim 3

In the set-reset circuit as claimed in claim 1 wherein said first and second transistors are insulated-gate field-effect transistors; wherein said first transistor is of one conductivity type and said second transistor is of complementary conductivity type; and wherein said coupling means is a transmission gate means comprising first and second insulated-gate field-effect transistors of first and second conductivity type, respectively.

Claim 4

In the set-reset circuit as claimed in claim 1 wherein said first and second transistors are of the same conductivity type; and wherein said coupling means is a transmission gate means.

Claim 5

The combination comprising: a data input point; first and second transmission gates; first and second data storage devices, each device having an input and an output; means connecting said first transmission gate between said data input point and the iNput of said first device; means connecting said second transmission gate between the output of said first device and the input of said second device; first and second points for the application thereto of first and second operating potentials, respectively; first and second transistors directly connected between the input of said first device and said first and second points, respectively; means coupled to said first and second transistors for selectively turning on one of said first and second transistors for setting said first device to one of first and second storage conditions, respectively; and means for enabling said second transmission gate and disabling said first transmission gate, concurrently with the turn on of one of said first and second transistors.

Claim 6

The combination comprising: a data input point; first and second transmission gates; first and second data storage devices, each device having an input and an output; means connecting said first transmission gate between said data input point and the iNput of said first device; means connecting said second transmission gate between the output of said first device and the input of said second device; first and second points for the application thereto of first and second operating potentials, respectively; first and second transistors directly connected between the input of said first device and said first and second points, respectively; means coupled to said first and second transistors for selectively turning on one of said first and second transistors for setting said first device to one of first and second storage conditions, respectively; and means for enabling said second transmission gate and disabling said first transmission gate, concurrently with the turn on of one of said first and second transistors.

Claim 7

The combination comprising: a data input point; first and second transmission gates; first and second data storage devices, each device having an input and an output; means connecting said first transmission gate between said data input point and the input of said first device; means connecting said second transmission gate between the output of said first device and the input of said second device; first and second points for the application thereto of first and second operating potentials, respectively; a set input terminal, a reset input terminal and a clock input terminal for the application thereto of set, reset, and clock signals, respectively; first and second transistors directly connected between the input of said first device and said first and second points, respectively; means coupling said set terminal to said first transistor for setting said first device to a first storage condition in response to a set signal; means coupling said reset terminal to said second transistor for setting said first device to a second storage condition in response to a reset signal; and gating means coupled between said set, reset, and clock terminals and said first and second transmission gates for enabling said first transmission gate during a first time interval and then enabling said second transmission gate during a succeeding time interval in the absence of set and reset signals, and responsive to the presence of one of said set and reset signals for disabling said first transmission gate and enabling said second transmission gate.

Claim 8

The combination comprising: a data input point; first and second transmission gates; first and second data storage devices, each device having an input and an output; means connecting said first transmission gate between said data input point and the input of said first device; means connecting said second transmission gate between the output of said first device and the input of said second device; first and second points for the application thereto of first and second operating potentials, respectively; a set input terminal, a reset input terminal and a clock input terminal for the application thereto of set, reset, and clock signals, respectively; first and second transistors directly connected between the input of said first device and said first and second points, respectively; means coupling said set terminal to said first transistor for setting said first device to a first storage condition in response to a set signal; means coupling said reset terminal to said second transistor for setting said first device to a second storage condition in response to a reset signal; and gating means coupled between said set, reset, and clock terminals and said first and second transmission gates for enabling said first transmission gate during a first time interval and then enabling said second transmission gate during a succeeding time interval in the absence of set and reset signals, and responsive to the presence of one of said set and reset signals for disabling said first transmission gate and enabling said second transmission gate.