Patent US3813610A successfully refreshed from Google Patents.
US3813610A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase-locked loop in which frequency divider ratios are altered to obtain rapid lock-in
Assignee: Individual
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Filing: 1973-02-14
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Granted: 1974-05-28
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Expires: 1993-02-14
Abstract
Abstract A phase locked loop for maintaining a voltage controlled oscillator within the locked-in range by means of excess pulse detectors provided for both high or low frequency deviations which function to significantly alter the dividing ratios of the dividing circuits respectively coupled to the voltage controlled oscillator and the standard signal oscillator to effect a rapid return to the locked-in state.
Inventors
- 👤 M Kimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 10:35
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/197; H03L7/1972
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
322 words
A phase locked loop system for maintaining a predetermined frequency output comprising: first voltage controlled oscillator means for generating an output signal whose frequency is dependent upon the level of a d.c. voltage applied to its input; second oscillator means for generating an output signal of a fixed frequency; first and second frequency divider means each respectively coupled to the outputs of said first and second oscillator means; phase comparator means having first and second inputs and first and second outputs; said first and second inputs being respectively coupled to the outputs of said first and second divider means; said phase comparator means being adapted to generate a square pulse signal at said first output wherein the pulse width of said square pulses is a function of the phase relationship between the signals applied to said first and second inputs; filter means coupled to said first output for converting said square pulses into a d.c. signal the level of which is a function of the pulse width of said square pulses, said d.c. signal being coupled to the input of said first oscillator means for controlling the frequency of said first oscillator means; first excess pulse detector means having inputs coupled to one output of said phase comparator means and the output of one of said divider means for generating a first output signal when the output frequency of said first oscillator means deviates in one direction from the desired predetermined frequency; said one of said divider means having at least one set input for altering the dividing ratio of said divider means upon the detection of an excess pulse; means coupled between said excess pulse detector means and the set input terminal of said one of said divider means for altering said dividing ratio; said one divider means being adapted to apply its output to said phaSe comparator means for alterning the d.c. level signal applied to said first oscillator means.
Claim 2
Dependent Claim
322 words
A phase locked loop system for maintaining a predetermined frequency output comprising: first voltage controlled oscillator means for generating an output signal whose frequency is dependent upon the level of a d.c. voltage applied to its input; second oscillator means for generating an output signal of a fixed frequency; first and second frequency divider means each respectively coupled to the outputs of said first and second oscillator means; phase comparator means having first and second inputs and first and second outputs; said first and second inputs being respectively coupled to the outputs of said first and second divider means; said phase comparator means being adapted to generate a square pulse signal at said first output wherein the pulse width of said square pulses is a function of the phase relationship between the signals applied to said first and second inputs; filter means coupled to said first output for converting said square pulses into a d.c. signal the level of which is a function of the pulse width of said square pulses, said d.c. signal being coupled to the input of said first oscillator means for controlling the frequency of said first oscillator means; first excess pulse detector means having inputs coupled to one output of said phase comparator means and the output of one of said divider means for generating a first output signal when the output frequency of said first oscillator means deviates in one direction from the desired predetermined frequency; said one of said divider means having at least one set input for altering the dividing ratio of said divider means upon the detection of an excess pulse; means coupled between said excess pulse detector means and the set input terminal of said one of said divider means for altering said dividing ratio; said one divider means being adapted to apply its output to said phaSe comparator means for alterning the d.c. level signal applied to said first oscillator means.
Claim 3
Dependent Claim
95 words
The system of claim 1 further comprising second excess pulse detector means having inputs coupled to the output of the remaining one of said divider means and the second output of said phase comparator means for generating a second output signal when the output frequency of said first oscillator means deviates in a second direction from the desired predetermined frequency; the remaining one of said divider means having a set input terminal coupled to the output of said second excess pulse detector means for altering its dividing ratio upon receipt of said second output signal.
Claim 4
Dependent Claim
82 words
The system of claim 2 wherein said first divider means is a programmable divider having a plurality of flip-flop stages each stage having a trigger input, set input and output terminals, the trigger input terminals of each stage being coupled to an output terminal of the preceeding stage; the trigger input of the first stage being coupled to the output of said first oscillator means, and means coupling the output of the last stage to one input of said phase comparator means.
Claim 5
Dependent Claim
73 words
The system of claim 2 wherein said second divider means comprises a plurality of fixed divider stages and a variable divider stage; said variable divider stage comprising a flip-flop having a trigger input, a set input and an output; said trigger input being coupled to the output of at least one of said fixed divider stages and said set input terminal being coupled to the output of said second excess pulse detector means.
Claim 6
Dependent Claim
50 words
The system of claim 3 further comprising gate means coupled between said first divider means and said phase comparator means for generating a narrow pulse applied to said first excess pulse detector means and said phase comparator means upon termination of the output signal developed by said first divider means.
Claim 7
Dependent Claim
50 words
The system of claim 4 further comprising gate means coupled between said second divider means and said phase comparator means for generating a narrow pulse applied to said second excess pulse detector means and said phase comparator means upon termination of the output signal developed by said first divider means.
Claim 8
Dependent Claim
120 words
The system of claim 3 wherein said means coupled between said first excess pulse detector means and said first divider means comprises a plurality of two input gates a first input of each of said gates being coupled in common to the output of said first excess pulse detector means; a plurality of switch means each operable between an open and a closed position for selectively coupling each of the remaining inputs of said gates to one output of said phase comparator means; the outputs of said gates being coupled to the set input terminals of selected ones of said flip-flop stages for altering the dividing ratio of those flip-flop stages whose associated switch means are in the closed position.
Claim 9
Dependent Claim
36 words
The system of claim 7 wherein the set input terminal of at least one of said flip-flop stages of said first divider means is directly coupled to the output of said first excess pulse detector means.
Claim 10
Dependent Claim
22 words
The system of claim 5 further comprising inverter means coupled between the output of said gate means and said phase comparator means.
Claim 11
Dependent Claim
22 words
The system of claim 6 further comprising inverter means coupled between the output of said gate means and said phase comparator means.
References Cited (Backward Citations)
US3534285A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-05-27 | 1977-11-26 | 1978-05-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-05-27 | 1981-11-26 | 1982-05-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-05-27 | 1985-11-26 | 1986-05-28 | $7700.00 | Window Closed / Lapsed |