Patent US3816758A successfully refreshed from Google Patents.
US3816758A
Expired / Lapsed
US
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Digital logic circuit
Assignee: International Business Machines Corp
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Filing: 1973-03-15
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Granted: 1974-06-11
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Expires: 1993-03-15
Abstract
Abstract A monolithic semiconductor circuit comprises a lateral PNP transistor and an inversely operated vertical NPN transistor. The lateral transistor is formed by a pair of mutually spaced P-type regions diffused in an N-type semiconductor body. The collector region has diffused therein a region of N-type and constituting the collector of the vertical transistor. The semi-conductor body constitutes the base region of the lateral transistor and the emitter region of the vertical transistor.
Inventors
- 👤 H Berger
- 👤 S Wiedmann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 06:23
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/63; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4113; G11C11/413; G11C11/414; G11C11/415; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/091; H10B; H10B10/00; H10B10/10; H10D84/65
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
98 words
A digital logic circuit comprising a first transistor of a predetermined conductivity type and having an emitter, a base and a collector, a second transistor of the opposite conductivity type and having an emitter, a base and a collector, an input adapted to receive a digital logic signal, an output, a current source, means connecting said first transistor emitter to said current source, means connecting said first transistor base to said second transistor emitter, means connecting said first transistor collector and said second transistor base to said input, and means connecting said second transistor collector to said output.
Claim 2
Dependent Claim
98 words
A digital logic circuit comprising a first transistor of a predetermined conductivity type and having an emitter, a base and a collector, a second transistor of the opposite conductivity type and having an emitter, a base and a collector, an input adapted to receive a digital logic signal, an output, a current source, means connecting said first transistor emitter to said current source, means connecting said first transistor base to said second transistor emitter, means connecting said first transistor collector and said second transistor base to said input, and means connecting said second transistor collector to said output.
Claim 3
Dependent Claim
40 words
A pair of digital logic circuits each as recited in claim 1, means connecting said first transistor emitters of both circuits to each other, and means connecting said outputs of both circuits to each other to provide a common output.
Claim 4
Dependent Claim
26 words
A NOR digital logic gate comprising a pair of digital logic circuits each as recited in claim 1, and means dot-ORing said outputs to each other.
Claim 5
Dependent Claim
26 words
A pair of digital logic circuits each as recited in claim 1, and conductor means connecting said outputs of both circuits to a common output node.
Claim 6
Dependent Claim
98 words
A digital logic circuit comprising a first transistor of a predetermined conductivity type and having a base and a collector, a second transistor of the opposite conductivity type and having an emitter, a base and a collector, a reference voltage source, an input adapted to receive a digital logic signal, an output, means connecting said first transistor base to said reference voltage source, means connecting said first transistor collector and said second transistor base to said input, means connecting said second transistor emitter to said reference voltage source, and means connecting said second transistor collector to said output.
Claim 7
Dependent Claim
98 words
A digital logic circuit comprising a first transistor of a predetermined conductivity type and having a base and a collector, a second transistor of the opposite conductivity type and having an emitter, a base and a collector, a reference voltage source, an input adapted to receive a digital logic signal, an output, means connecting said first transistor base to said reference voltage source, means connecting said first transistor collector and said second transistor base to said input, means connecting said second transistor emitter to said reference voltage source, and means connecting said second transistor collector to said output.
Claim 8
Dependent Claim
23 words
A pair of digital logic circuits each as recited in claim 5, and means connecting said outputs of both circuits to each other.
Claim 9
Dependent Claim
26 words
A NOR digital logic gate comprising a pair of digital logic circuits each as recited in claim 5, and means dot-ORing said outputs to each other.
Claim 10
Dependent Claim
26 words
A pair of digital logic circuits each as recited in claim 5, and conductor means connecting said outputs of both circuits to a common output mode.
Claim 11
Dependent Claim
123 words
A digital logic circuit comprising a first transistor of a predetermined conductivity type and having an emitter, a base and a collector, a second transistor of the opposite conductivity type and having an emitter, a base and a collector, a reference voltage source, a first input for connections to a substantially constant current source, a second input adapted to receive a digital logic signal, an output, means connecting said first transistor emitter to said first input, means connecting said first transistor base to said reference voltage source, means connecting said first transistor collector and said second transistor base to said second input, means connecting saId second transistor emitter to said reference voltage source, and means connecting said second transistor collector to said output.
Claim 12
Dependent Claim
123 words
A digital logic circuit comprising a first transistor of a predetermined conductivity type and having an emitter, a base and a collector, a second transistor of the opposite conductivity type and having an emitter, a base and a collector, a reference voltage source, a first input for connections to a substantially constant current source, a second input adapted to receive a digital logic signal, an output, means connecting said first transistor emitter to said first input, means connecting said first transistor base to said reference voltage source, means connecting said first transistor collector and said second transistor base to said second input, means connecting saId second transistor emitter to said reference voltage source, and means connecting said second transistor collector to said output.
Claim 13
Dependent Claim
39 words
A pair of digital logic circuits each as recited in claim 9, means connecting said first inputs of both circuits to each other, and means connecting said outputs of both circuits to each other to provide a common output.
Claim 14
Dependent Claim
26 words
A NOR digital logic gate comprising a pair of digital logic circuits each as recited in claim 9, and means dot-ORing said outputs to each other.
Claim 15
Dependent Claim
26 words
A pair of digital logic circuits each as recited in claim 9, and conductor means connecting said outputs of both circuits to a common output node.
Claim 16
Dependent Claim
81 words
A logic circuit comprising a first transistor of a predetermined conductivity type and having an emitter, a base, and a collector, a second transistor of the opposite conductivity type and having an emitter, a base, and collector, means connecting said first transistor collector to said second transistor base, means connecting said first transistor base to said second transistor emitter, an input connected to said first transistor collector and said second transistor base, and an output connected to said second transistor collector.
Claim 17
Dependent Claim
81 words
A logic circuit comprising a first transistor of a predetermined conductivity type and having an emitter, a base, and a collector, a second transistor of the opposite conductivity type and having an emitter, a base, and collector, means connecting said first transistor collector to said second transistor base, means connecting said first transistor base to said second transistor emitter, an input connected to said first transistor collector and said second transistor base, and an output connected to said second transistor collector.
Claim 18
Dependent Claim
35 words
A logic circuit as recited in claim 13 and comprising a current source connected to said first transistor emitter, and a source of fixed potential connected to said first transistor base and second transistor emitter.
Claim 19
Dependent Claim
25 words
A pair of logic circuits each as recited in claim 13, and means connecting the outputs of both logic circuits to provide a NOR/NAND circuit.
Claim 20
Dependent Claim
34 words
A pair of logic circuits each as recited in claim 13, and means connecting the output of one circuit to the input of the other circuit so as to connect the circuits in cascade.
Claim 21
Dependent Claim
88 words
Logic circuitry comprising a first pair of logic circuits each as recited in claim 13, first output means connecting the outputs of said first pair of circuits to provide a first NOR/NAND circuit, a second pair of logic circuits each as recited in claim 14, second output means connecting the outputs of said second pair of circuits to provide a second NOR/NAND circuit, and means connecting said first output means to an input of said second pair of circuits so as to connect said NOR/NAND circuits in cascade.
References Cited (Backward Citations)
US2820199A
Cited
US3534281A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-06-10 | 1977-12-10 | 1978-06-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-06-10 | 1981-12-10 | 1982-06-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-06-10 | 1985-12-10 | 1986-06-11 | $7700.00 | Window Closed / Lapsed |