Patent US3830983A successfully refreshed from Google Patents.
US3830983A
Expired / Lapsed
US
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Communication system interlock arrangement
Assignee: AG Communication Systems Corp
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Filing: 1972-12-04
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Granted: 1974-08-20
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Expires: 1992-12-04
Abstract
Abstract Control transfer arrangement for a communication system including a switching system wherein a marker applies temporary hold signals to establish temporary connections between line circuits and register junctors while also transmitting information signals to a data processor. Logic circuits are provided for responding to instruction signals from the data processor and to signals from the register junctors to develop sustaining hold signals which are applied to sustain connections through the switching system and to permit release of the marker after each connection is established. Important features relate to the form of the logic circuits, to the use of memory means and multiplex circuitry to permit use of common logic circuits and to the provision of timer means for operating trouble indicating means when both conditions required for a sustaining hold signal are not established within a certain length of time after one is established.
Inventors
- 👤 J Eddy
- 👤 S Puccini
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 10:46
CPC Classifications
H; H04; H04Q; H04Q3/00; H04Q3/42; H04Q3/54; H04Q3/545
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
177 words
In a communication system including a switching network having first and second groups of terminaLs, marker means for applying temporary hold signals to establish temporary connections between terminals of said first group and terminals of said second group and for transmitting information signals identifying said temporary connections, and data processing means for receiving said information signals and developing instruction signals in response thereto, a plurality of junctor means connected to said second group of terminals, each of said junctor means including holding means for responding to a temporary hold signal from said marker means to maintain a connection thereto through said switching network and further including signalling means responsive to establishment of a connection thereto, and transfer control means including logic circuit means for responding to instruction signals from said data processing means and to signals from said signalling means of said junctor means to develop sustaining hold signals, and means for applying said sustaining hold signals to said junctor means to sustain connections thereto and permit release of said temporary hold signals from said marker means.
Claim 2
Dependent Claim
177 words
In a communication system including a switching network having first and second groups of terminaLs, marker means for applying temporary hold signals to establish temporary connections between terminals of said first group and terminals of said second group and for transmitting information signals identifying said temporary connections, and data processing means for receiving said information signals and developing instruction signals in response thereto, a plurality of junctor means connected to said second group of terminals, each of said junctor means including holding means for responding to a temporary hold signal from said marker means to maintain a connection thereto through said switching network and further including signalling means responsive to establishment of a connection thereto, and transfer control means including logic circuit means for responding to instruction signals from said data processing means and to signals from said signalling means of said junctor means to develop sustaining hold signals, and means for applying said sustaining hold signals to said junctor means to sustain connections thereto and permit release of said temporary hold signals from said marker means.
Claim 3
Dependent Claim
55 words
In a system as defined in claim 1, a register subsystem including said junctors and further including memory means, writing means for writing signals into said memory means including signals from said signalling means of said junctor means, and reading means for reading out stored signals from said memory means to said logic circuit means.
Claim 4
Dependent Claim
49 words
In a system as defined in claim 2, said writing means being additionally operative for writing said instruction signals from said data processing means into said memory means, and said reading means being operative for reading out stored instruction signals from said memory means to said logic circuit means.
Claim 5
Dependent Claim
42 words
In a system as defined in claim 1, multiplex means for transmitting signals from said signalling means of said junctor means to said logic circuit means and for transmitting said sustaining hold signals from said logic circuit means to said junctor means.
Claim 6
Dependent Claim
29 words
In a system as defined in claim 4, said multiplex means being additionally operative for transmitting said instruction signals from said data processing means to said logic circuit means.
Claim 7
Dependent Claim
69 words
In a system as defined in claim 4, a register subsystem including said junctors and further including memory means, writing means operable in conjunction with said multiplex means for writing signals into said memory means including signals from said signalling means of said junctor means, and reading means operable in conjunction with said multiplex means for reading out stored signals from said memory means to said logic circuit means.
Claim 8
Dependent Claim
59 words
In a system as defined in claim 6, said writing means being additionally operative in conjunction with said multiplex means for writing signals from said data processing means into said memory means, and said reading means being operative in conjunction with said multiplex means for reading out stored instruction signals from said memory means to said logic circuit means.
Claim 9
Dependent Claim
51 words
In a system as defined in claim 1, said logic circuit means comprising AND gate means having inputs responsive to said signals from said signalling means of said junctor means and instruction signals from said data processing means and operative to develop and output signal only upon coincidence of said signals.
Claim 10
Dependent Claim
29 words
In a system as defined in claim 8, a carry buffer latch circuit responsive to said output signal from said AND gate means for developing said sustaining hold signals.
Claim 11
Dependent Claim
135 words
In a system as defined in claim 8, multiplex means for transmitting signals from said signalling means of said junctor means and instruction signals from said data processing means to said logic circuit means and sustaining hold signals from said logic circuit means to said junctor means, timing generator means associated with said multiplex means and operative to develop signals assigning a particular time slot to each of said junctor means and assigning a certain sub-time slot of eAch junctor means time slot for processing of signals from said signalling means of said junctor means and instruction signals from said data processing means, said AND gate means having an input responsive to said certain sub-time slot signal and being operative to develop an output signal only upon application of said certain sub-time slot signal thereto.
Claim 12
Dependent Claim
86 words
In a system as defined in claim 10, process sequence state control means for controlling the processing of signals through said switching network and operative to develop a certain process state signal for processing of signals from said signalling means of said junctor means and said instruction signals from said data processing means, said AND gate means having an additional input responsive to said certain process state signal and being operative to develop an output signal only upon application of said certain process state signal thereto.
Claim 13
Dependent Claim
79 words
In a system as defined in claim 11, a register subsystem including said junctors and further including memory means, writing means operable in conjunction with said multiplex means for writing signals into said memory means including signals, instruction signals from said data processing means and process state signals from said process sequence state control means, and reading means operable in conjunction with said multiplex means for reading out stored signals from said memory means to said logic circuit means.
Claim 14
Dependent Claim
113 words
In a system as defined in claim 1, timer means arranged to develop an output signal after a certain elapsed time after initiating operation thereof, means for initiating operation of said timer means in response to only one and not both of first and second signals, said first signal being a signal from said signalling means of a certain junctor means and said second signal being an instruction signal from said data processing means corresponding to said certain junctor means, means for resetting said timer means in response to coincidence of neither or both of said first and second signals, and trouble indicating means responsive to an output signal from said timer means.
Claim 15
Dependent Claim
49 words
In a system as defined in claim 1, including a plurality of line circuits connected to said first group of terminals, each one of said connections including a transmission path operative for transmission of dial pulses from a line circuit to a junctor means and the signalling means thereof.
Claim 16
Dependent Claim
77 words
In a system as defined in claim 14, said signalling means including bistable means shifted from a first state to a second state in response to completion of a transmission path from a line circuit to the associated junctor means and shifted from said first state to said second state by momentary dial pulse interruptions of said path, said logic circuit means being responsive only to signals generated by said bistable means in said second state thereof.
References Cited (Backward Citations)
US3564149A
Cited
US3624305A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-08-19 | 1978-02-18 | 1978-08-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-08-19 | 1982-02-18 | 1982-08-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-08-19 | 1986-02-18 | 1986-08-20 | $7700.00 | Window Closed / Lapsed |