Patent US3838293A successfully refreshed from Google Patents.
US3838293A
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US
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Three clock phase, four transistor per stage shift register
Assignee: NCR Voyix Corp
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Filing: 1973-10-11
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Granted: 1974-09-24
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Expires: 1993-10-11
Abstract
Abstract In order to achieve increased packing density, a simplified ratioless shift register stage is provided which utilizes only four transistors per stage and requires only three clock signals. A stage input signal is clocked through a transistor dynamic inverter with a phi 1 clock signal. The information is then coupled through a single transistor inverter with a phi 2 clock signal which is present concurrently with and also extends beyond phi 1. After the termination of phi 2 the information is coupled to a stage output point through a single transistor switch actuated by a phi 3 clock signal.
Inventors
- 👤 R Shah
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 06:28
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/18; G11C19/182; G11C19/184
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
302 words
In a logic system including means for developing first, second, and third clock signals, the first and second clock signals being true concurrently, the second clock signal being true after the first clock signal becomes false, and the third clock signal being true only when the first and second clock signals are false, an integrated circuit shift register consisting of a plurality of serially coupled, identical stages, each said stage comprising: A. a first transistor switch; B. a second transistor switch; C. said first and second transistor switches connected in series, each of said first and second transistor switches having a first electrode connected to receive the first clock signal, second electrodes of said first and second transistor switches being connected together, a control electrode of said first transistor switch being coupled to receive a logical input signal, a control electrode of said second transistor switch being connected to receive and respond to the first clock signal; D. a third transistor switch; E. a fourth transistor switch; F. a first electrode of said third transistor switch being connected to receive the second clock signal, a second electrode of said third transistor switch being connected to a first electrode of said fourth transistor switch, a second electrode of said fourth transistor switch effecting a stage output terminal; G. a control electrode of said third transistor switch being connected to said second electrodes of said first and second transistors, a control electrode of said fourth transistor switch being connected to receive and respond to the third clock signal; and H. first, second, and third capacitive temporary storage means connected, respectively, between said control electrode of said first transistor switch and ground, between said control electrode of said third transistor switch and ground, and between said first electrode of said fourth transistor switch and ground.
Claim 2
Dependent Claim
302 words
In a logic system including means for developing first, second, and third clock signals, the first and second clock signals being true concurrently, the second clock signal being true after the first clock signal becomes false, and the third clock signal being true only when the first and second clock signals are false, an integrated circuit shift register consisting of a plurality of serially coupled, identical stages, each said stage comprising: A. a first transistor switch; B. a second transistor switch; C. said first and second transistor switches connected in series, each of said first and second transistor switches having a first electrode connected to receive the first clock signal, second electrodes of said first and second transistor switches being connected together, a control electrode of said first transistor switch being coupled to receive a logical input signal, a control electrode of said second transistor switch being connected to receive and respond to the first clock signal; D. a third transistor switch; E. a fourth transistor switch; F. a first electrode of said third transistor switch being connected to receive the second clock signal, a second electrode of said third transistor switch being connected to a first electrode of said fourth transistor switch, a second electrode of said fourth transistor switch effecting a stage output terminal; G. a control electrode of said third transistor switch being connected to said second electrodes of said first and second transistors, a control electrode of said fourth transistor switch being connected to receive and respond to the third clock signal; and H. first, second, and third capacitive temporary storage means connected, respectively, between said control electrode of said first transistor switch and ground, between said control electrode of said third transistor switch and ground, and between said first electrode of said fourth transistor switch and ground.
Claim 3
Dependent Claim
37 words
The integrated circuit shift register stage of claim 1 in which said first, second, and third capacitive temporary storage means each comprise the inherent capacitance between a conductive lead in the circuit and the integrated circuit substrate.
Claim 4
Dependent Claim
26 words
The integrated circuit shift register of claim 2 in which each of said first, second, third, and fourth transistor switches comprises an MOS field effect transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-09-23 | 1978-03-25 | 1978-09-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-09-23 | 1982-03-25 | 1982-09-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-09-23 | 1986-03-25 | 1986-09-24 | $7700.00 | Window Closed / Lapsed |