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US3881100A
Expired / Lapsed
US
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Real-time fourier transformation apparatus
Assignee: Raytheon Co
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Filing: 1973-10-30
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Granted: 1975-04-29
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Expires: 1993-10-30
Abstract
Abstract An apparatus for performing real-time Fourier transformation of a time varying signal by taking successive digital samples in a shift register means and repeatedly transforming preselected pairs of said samples as the samples are progressively shifted down the register. The successive samples are ordered in the register in a binary sequence from 0 to 2n-1 while the pairs are selected when the binary distance between them is equal to 2n m, m being the transformation number, each pair xa,m, Xb,m being related to its transformed magnitude Xa,m 1 and Xb,m 1 by the relations
Inventors
- 👤 George A Works
- 👤 Harry Vickers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 14:14
CPC Classifications
G; G06; G06F; G06F17/00; G06F17/10; G06F17/14; G06F17/141; G06F17/142
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
83 words
A system for performing a Fourier transform comprising a plurality of serially coupled computational stages, each stage comprising in combination: means for performing arithmetic operations upon sets of data; means for storing at least portions of said sets; means for coupling at least portions of the results of said arithmetic operations upon said sets to said storing means; and said system further comprising single means for controlling each of said coupling means, said controlling means operating independently from any stored set of instructions.
Claim 2
Independent Claim
83 words
A system for performing a Fourier transform comprising a plurality of serially coupled computational stages, each stage comprising in combination: means for performing arithmetic operations upon sets of data; means for storing at least portions of said sets; means for coupling at least portions of the results of said arithmetic operations upon said sets to said storing means; and said system further comprising single means for controlling each of said coupling means, said controlling means operating independently from any stored set of instructions.
Claim 3
Dependent Claim
28 words
The combination of claim 1 wherein said means for performing arithmetic operations comprises means for performing at least a portion of a discrete Fourier transform upon said sets.
Claim 4
Dependent Claim
14 words
The combination of claim 2 wherein said storing means comprises shift register storage means.
Claim 5
Dependent Claim
13 words
The combination of claim 2 wherein said storing means comprises an addressable register.
Claim 6
Dependent Claim
14 words
The combination of claim 2 wherein said controlling means comprises a cyclical binary counter.
Claim 7
Dependent Claim
70 words
In combination: a single means for providing a cyclic count; a plurality of memory means; and arithmetic computation means coupled to each of said memory means for calculating a discrete Fourier transformation upon a set of data samples, said computation means including means for weighting at least some of said samples, said plurality of memory means and said arithmetic computation means all being synchronized by said single count providing means.
Claim 8
Dependent Claim
70 words
In combination: a single means for providing a cyclic count; a plurality of memory means; and arithmetic computation means coupled to each of said memory means for calculating a discrete Fourier transformation upon a set of data samples, said computation means including means for weighting at least some of said samples, said plurality of memory means and said arithmetic computation means all being synchronized by said single count providing means.
Claim 9
Dependent Claim
18 words
The combination of claim 6 wherein said means for providing a cyclic count comprises a cyclical binary counter.
Claim 10
Dependent Claim
13 words
The combination of claim 6 wherein said memory means comprises shift register means.
Claim 11
Dependent Claim
13 words
The combination of claim 7 wherein said memory means comprises an addressable register.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-04-28 | 1978-10-28 | 1979-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-04-28 | 1982-10-28 | 1983-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-04-28 | 1986-10-28 | 1987-04-29 | $7700.00 | Window Closed / Lapsed |