Patent US3924068A successfully refreshed from Google Patents.
US3924068A
Expired / Lapsed
US
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Low distortion receiver for bi-level baseband PCM waveforms
Assignee: National Aeronautics and Space Administration
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Filing: 1974-04-26
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Granted: 1975-12-02
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Expires: 1994-04-26
Abstract
Abstract Disclosed is an improved low distortion asynchronous receiver designed to receive balanced, differential signals from a transmission line, recover and reconstruct a positive logic level signal from the received signals and supply a suitable unipolar pulse code modulated (pcm) output waveform to a conventional sync detector/data decoder for further processing. A hybrid transformer couples the differential signals appearing on the transmission line into the receiver as a double-ended input referenced to the receiver ground. The double-ended signals are comprised of two signals of equal amplitude and opposite polarity. Each of the two signals is applied to a separate lowpass filter network to provide a standard waveform transition characteristic. Each filtered signal is supplied to a threshold detection circuit comprising a differential comparator, a NAND gate and a voltage divider network. The detection circuit provides a stable threshold level for converting the filtered line signal to positive logic levels. A hysteresis characteristic of the detector circuit prevents undesired output transitions when the filtered signal amplitudes are near the threshold level. Output circuitry provides waveform shaping in the output signals from the detection circuit to remove systematic waveform distortion. Included with the output circuitry is a rest and initialization circuit for ensuring a proper output level.
Inventors
- 👤 James C Administrator Fletcher
- 👤 George E Proch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:51
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4904
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
324 words
A receiver for a zero direct current input signal transmitted as the output signal from a remotely located transmitter comprising: a. duplicating and inverting means for providing an inverted signal which has the same amplitude as that of the receiver input signal but is 180* out-of-phase with said receiver input signal; b. processing means in said receiver for processing said receiver input signal and said inverted signal for symmetrically processing positive and negative going transitions of said receiver input signal; c. filter means including frequency responsive circuit means in said processing means fr symmetrically filtering and band limiting said receiver input and said inverted signal; d. threshold detector means for providing first and second detector signals wherein said first detector signal is representative of the occurrence of one or more signal parameters in said filtered receiver input signal and in said filtered inverted signal which reach predetermined values and wherein said second detector signal is representative of the absence of the occurrence thereof; e. hysteresis means included with said threshold detector means for causing said threshold detector means to maintain said first detector or said second detector output once formed until the one or more parameters of said filtered receiver input signal and said filtered inverted signal reach predetermined values which are different from those causing the formation of said detector signals; f. output circuit means selectively responsive to at least one of said first and second detector signals for reproducinG an undistorted signal directly corresponding to the input signal supplied to said transmitter, said output circuit means including pulse duration restoring means for providing pulse durations in one or more of said first and second detector signals corresponding to those durations of the pulses in said receiver input signal and said inverted signal which produced said detector signals, said pulse duration restoring means including latch means responsive to the transition from said second to said first detector signal to produce said undistorted signal.
Claim 2
Dependent Claim
324 words
A receiver for a zero direct current input signal transmitted as the output signal from a remotely located transmitter comprising: a. duplicating and inverting means for providing an inverted signal which has the same amplitude as that of the receiver input signal but is 180* out-of-phase with said receiver input signal; b. processing means in said receiver for processing said receiver input signal and said inverted signal for symmetrically processing positive and negative going transitions of said receiver input signal; c. filter means including frequency responsive circuit means in said processing means fr symmetrically filtering and band limiting said receiver input and said inverted signal; d. threshold detector means for providing first and second detector signals wherein said first detector signal is representative of the occurrence of one or more signal parameters in said filtered receiver input signal and in said filtered inverted signal which reach predetermined values and wherein said second detector signal is representative of the absence of the occurrence thereof; e. hysteresis means included with said threshold detector means for causing said threshold detector means to maintain said first detector or said second detector output once formed until the one or more parameters of said filtered receiver input signal and said filtered inverted signal reach predetermined values which are different from those causing the formation of said detector signals; f. output circuit means selectively responsive to at least one of said first and second detector signals for reproducinG an undistorted signal directly corresponding to the input signal supplied to said transmitter, said output circuit means including pulse duration restoring means for providing pulse durations in one or more of said first and second detector signals corresponding to those durations of the pulses in said receiver input signal and said inverted signal which produced said detector signals, said pulse duration restoring means including latch means responsive to the transition from said second to said first detector signal to produce said undistorted signal.
Claim 3
Dependent Claim
16 words
A receiver as defined in claim 1 wherein said duplicating and inverting means includes a transformer.
Claim 4
Dependent Claim
84 words
A receiver as defined in claim 2 wherein: a. said remotely located transmitter is coupled with a transmission line; and b. said transformer is coupled through its primary winding with said transmission line and includes two secondary windings, one of said secondary windings reproducing the signal on said transmission line to provide said receiver input signal and the other secondary winding forming a signal which has the same amplitude as that of the line signal but is 180* out-of-phase to provide said inverted signal.
Claim 5
Dependent Claim
93 words
A receiver as defined in claim 1 wherein: a. said threshold detector means includes amplitude responsive means for providing said first detector signal when the amplitudes of said filtered receiver input signal and said inverted signal are more positive than a predetermined positive threshold value; and b. said hysteresis means includes means for causing the formation of said second detector signal when the amplitudes of said filtered receiver input signal and said inverted signal become less positive than a predetermined positive value which is less positive than that of said positive threshold value.
Claim 6
Dependent Claim
51 words
A receiver as defined in claim 1 further including receiver initialization and reset means responsive to the occurrence of predetermined power supply or data conditions for imposing predetermined initial conditions upon said receiver to prepare said receiver to receive data following the occurrence of said predetermined power supply or data conditions.
Claim 7
Dependent Claim
89 words
A receiver as defined in claim 5 wherein said initialization and reset means includes a reset means comprising a resettable pulse counter connected with a pulse producing clock means, said counter including means for forming an internally generated reset pulse which is supplied to reset gate means when a predetermined number of pulses have been generated by said clock means, said threshold detector means being responsive to said internal reset pulse for causing said threshold detector means to form a selected one of said first or second detector signals.
Claim 8
Dependent Claim
22 words
A receiver as defined in claim 6 wherein said reset pulse causes said threshold detector means to form said second detector signal.
Claim 9
Dependent Claim
45 words
A receiver as defined in claim 5 wherein one or more said predetermined data conditions includes a synchronization signal comprising a positive and negative sync pulse with said predetermined initial condition occurring on the transition from said positive sync pulse to said negative sync pulse.
Claim 10
Dependent Claim
57 words
A receiver as defined in claim 6 wherein said receiver initialization and reset circuit means further includes means for accepting an externally generated reset pulse and said threshold detector means is responsive to said internal or said external reset pulse for causing said detector means to form a selected one of said first or second detector signals.
Claim 11
Dependent Claim
30 words
A receiver as defined in claim 9 wherein said reset gate means accepts said internal reset or said external reset pulse for imposing said predetermined initial conditions upon said receiver.
Claim 12
Dependent Claim
124 words
A receiver as defined in claim 10 wherein said threshold detector means further includes: a. first and second differential comparator means each having positive and negative inputs with said filtered receiver input signal supplied to the negative input of said first differential comparator means and said filtered inverted signal each supplied to the negative input of said second comparator means; b. first and second gate circuit means responsive to the output of said reset gate and to the output of said comparator means for producing said first and second detector signals; and c. feedback means responsive to said detector signals and applied to said positive inputs of said comparators for determining said threshold values at which said first and second detection signals are formed.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-12-01 | 1979-06-02 | 1979-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-12-01 | 1983-06-02 | 1983-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-12-01 | 1987-06-02 | 1987-12-02 | $7700.00 | Window Closed / Lapsed |