Patent US3943548A successfully refreshed from Google Patents.
US3943548A
Expired / Lapsed
US
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Semiconductor controlled rectifier
Assignee: Hitachi Ltd
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Filing: 1974-02-05
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Granted: 1976-03-09
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Expires: 1994-02-05
Abstract
Abstract A semiconductor controlled rectifier comprising a four-layer semicondcutor substrate of pnpn structure, a pair of main electrodes in contact with the outer p-type and n-type layers respectively, and a gate electrode in contact with one of the intermediate layers forming a pn junction between it and the outer layer adjacent thereto, wherein gate current supplied from the gate electrode flows into the outer layer adjacent to the intermediate layer having the gate electrode thereon across a portion of the pn junction which portion is parallel with the surface of the said outer layer in contact with the main electrode.
Inventors
- 👤 Yoshio Terasawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:27
CPC Classifications
H; H10; H10D; H10D99/00; H10D62/00; H10D62/10; H10D62/17
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
400 words
A semiconductor controlled rectifier comprising: a semiconductor substrate with first and second principal surfaces opposite each other, said semiconductor substrate including four continuous layers of alternately different conductivity types between said first and second principal surfaces so that pn junctions are formed between each two adjacent layers, the entire end of the pn junction formed between a first outermost layer and a first intermediate layer adjacent to said first outermost layer being exposed at said first principal surface, said first outermost layer and part of said first intermediate layer constituting said first principal surface, first and second auxiliary regions being formed in said first intermediate layer to the depth of said first outermost layer and having a conductivity type opposite that of said first intermediate layer, said first and second auxiliary regions being spaced apart from and facing each other and extending along the marginal edge of said first outermost layer and spaced apart from said first outermost layer and exposed at said first principal surface, said first outermost layer being closer to said first auxiliary region than to said second auxiliary region, third and fourth auxiliary regions being formed between said first outermost layer and said first auxiliary region in said first intermediate layer to the depth of said first outermost layer and having a conductivity type opposite that of said first intermediate layer, said third and fourth auxiliary regions being spaced apart from and facing each other and extending along the marginal edge of said first outermost layer and spaced apart from said first outermost layer and exposed at said first principal surface, said first outermost layer being closer to said third auxiliary region than to said fourth auxiliary region, and a second outermost layer constituting said second principal surface; a first main electrode in ohmic contact with said first outermost layer on said first principal surface; a second main electrode in ohmic contact with said second outermost layer on said second principal surface; a conductor in electrical contact with said first auxiliary region, said second auxiliary region and that portion of said first intermediate layer which lies between said first and second auxiliary regions on said first principal surface; and an auxiliary electrode in electrical contact with said third auxiliary region, said fourth auxiliary region and that portion of said first intermediate layer which lies between said third and fourth auxiliary regions on said first principal surface.
Claim 2
Dependent Claim
400 words
A semiconductor controlled rectifier comprising: a semiconductor substrate with first and second principal surfaces opposite each other, said semiconductor substrate including four continuous layers of alternately different conductivity types between said first and second principal surfaces so that pn junctions are formed between each two adjacent layers, the entire end of the pn junction formed between a first outermost layer and a first intermediate layer adjacent to said first outermost layer being exposed at said first principal surface, said first outermost layer and part of said first intermediate layer constituting said first principal surface, first and second auxiliary regions being formed in said first intermediate layer to the depth of said first outermost layer and having a conductivity type opposite that of said first intermediate layer, said first and second auxiliary regions being spaced apart from and facing each other and extending along the marginal edge of said first outermost layer and spaced apart from said first outermost layer and exposed at said first principal surface, said first outermost layer being closer to said first auxiliary region than to said second auxiliary region, third and fourth auxiliary regions being formed between said first outermost layer and said first auxiliary region in said first intermediate layer to the depth of said first outermost layer and having a conductivity type opposite that of said first intermediate layer, said third and fourth auxiliary regions being spaced apart from and facing each other and extending along the marginal edge of said first outermost layer and spaced apart from said first outermost layer and exposed at said first principal surface, said first outermost layer being closer to said third auxiliary region than to said fourth auxiliary region, and a second outermost layer constituting said second principal surface; a first main electrode in ohmic contact with said first outermost layer on said first principal surface; a second main electrode in ohmic contact with said second outermost layer on said second principal surface; a conductor in electrical contact with said first auxiliary region, said second auxiliary region and that portion of said first intermediate layer which lies between said first and second auxiliary regions on said first principal surface; and an auxiliary electrode in electrical contact with said third auxiliary region, said fourth auxiliary region and that portion of said first intermediate layer which lies between said third and fourth auxiliary regions on said first principal surface.
Claim 3
Dependent Claim
38 words
A semiconductor controlled rectifier as claimed in claim 1, wherein the lengths of said third and fourth auxiliary regions along the periphery of said first outermost layer are larger than those of said first and second auxiliary regions.
Claim 4
Dependent Claim
38 words
A semiconductor controlled rectifier as claimed in claim 1, wherein the lengths of said first and second auxiliary regions along the periphery of said first outermost layer are larger than those of said third and fourth auxiliary regions.
Claim 5
Dependent Claim
29 words
A semiconductor controlled rectifier as claimed in claim 3, wherein said third and fourth auxiliary regions are connected to each other at adjacent and spaced apart surface portions thereof.
Claim 6
Dependent Claim
30 words
A semiconductor controlled rectifier as claimed in claim 2, wherein said third and fourth auxiliary regions surround said first outermost layer along the marginal edge of said first outermost layer.
Claim 7
Dependent Claim
30 words
A semiconductor controlled rectifier as claimed in claim 3, wherein said first and second auxiliary regions surround said first outermost layer along the marginal edge of said first outermost layer.
Claim 8
Dependent Claim
29 words
A semiconductor controlled rectifier as claimed in claim 6, wherein said third and fourth auxiliary regions are connected to each other at adjacent and spaced apart surface portions thereof.
Claim 9
Dependent Claim
439 words
A semiconductor controlled rectifier comprising: a semiconductor substrate with first and second principal surface opposite each other, said semiconductor substrate including four continuous layers of alternately different conductivity types between said first and second principal surfaces so that pn junctions are formed between each two adjacent layers, a first outermost layer being constituted by a central section and a peripheral section surrounding said central section, the entire ends of pn junctions formed between said first outermost layer and a first intermediate layer adjacent said first outermost layer being exposed at said first principal surface, said central and peripheral sections of said first outermost layer being spaced apart from each other in said first intermediate layer, said first outermost layer and part of said first intermediate layer constituting said first principal surface, first and second auxiliary regions being formed between said central and peripheral sections of said first outermost layer in said first intermediate layer to the depth of said first outermost layer and having a conductivity type opposite to that of said first intermediate layer, said first and second auxiliary regions being spaced apart from and facing each other and extending annularly and continuously to partially surround said central section of said first outermost layer and spaced apart from said central section of said first outermost layer and exposed at said first principal surface, said first and second auxiliary regions being connected to each other at adjacent and spaced apart surface portions, a third annular auxiliary region being formed to the depth of said first outermost layer in a space in said first intermediate layer defined between said central and peripheral sections of said first outermost layer and the ends of said first and second auxiliary regions, said third auxiliary region being spaced apart from said first outermost layer and said first and second auxiliary region and having a conductivity type opposite to that of said first intermediate layer and exposed at said first principal surface, and a second outermost layer constituting said second principal surface; a first main electrode in ohmic contact with said first outermost layer on said first principal surface; a second main electrode in ohmic contact with said second outermost layer on said second principal surface; a conductor in electrical contact with said first auxiliary region, said second auxiliary region and that portion of said first intermediate layer which lies between said first and second auxiliary regions on said first principal surface; and an auxiliary electrode in electrical contact with said third auxiliary region and that portion of said first intermediate layer which is defined by said third auxiliary region on said first principal surface.
Claim 10
Dependent Claim
439 words
A semiconductor controlled rectifier comprising: a semiconductor substrate with first and second principal surface opposite each other, said semiconductor substrate including four continuous layers of alternately different conductivity types between said first and second principal surfaces so that pn junctions are formed between each two adjacent layers, a first outermost layer being constituted by a central section and a peripheral section surrounding said central section, the entire ends of pn junctions formed between said first outermost layer and a first intermediate layer adjacent said first outermost layer being exposed at said first principal surface, said central and peripheral sections of said first outermost layer being spaced apart from each other in said first intermediate layer, said first outermost layer and part of said first intermediate layer constituting said first principal surface, first and second auxiliary regions being formed between said central and peripheral sections of said first outermost layer in said first intermediate layer to the depth of said first outermost layer and having a conductivity type opposite to that of said first intermediate layer, said first and second auxiliary regions being spaced apart from and facing each other and extending annularly and continuously to partially surround said central section of said first outermost layer and spaced apart from said central section of said first outermost layer and exposed at said first principal surface, said first and second auxiliary regions being connected to each other at adjacent and spaced apart surface portions, a third annular auxiliary region being formed to the depth of said first outermost layer in a space in said first intermediate layer defined between said central and peripheral sections of said first outermost layer and the ends of said first and second auxiliary regions, said third auxiliary region being spaced apart from said first outermost layer and said first and second auxiliary region and having a conductivity type opposite to that of said first intermediate layer and exposed at said first principal surface, and a second outermost layer constituting said second principal surface; a first main electrode in ohmic contact with said first outermost layer on said first principal surface; a second main electrode in ohmic contact with said second outermost layer on said second principal surface; a conductor in electrical contact with said first auxiliary region, said second auxiliary region and that portion of said first intermediate layer which lies between said first and second auxiliary regions on said first principal surface; and an auxiliary electrode in electrical contact with said third auxiliary region and that portion of said first intermediate layer which is defined by said third auxiliary region on said first principal surface.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-03-09 | 1979-09-08 | 1980-03-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-03-09 | 1983-09-08 | 1984-03-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-03-09 | 1987-09-08 | 1988-03-09 | $7700.00 | Window Closed / Lapsed |