Patent US3965567A successfully refreshed from Google Patents.
US3965567A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for producing diffused contacted and surface passivated semiconductor chips for semiconductor devices
Assignee: Licentia Patent Verwaltungs GmbH
•
Filing: 1974-06-28
•
Granted: 1976-06-29
•
Expires: 1994-06-28
Abstract
Abstract A method for producing diffused, contacted and surface passivated semiconductor chips for semiconductor devices, wherein after producing a semiconductor wafer with a given arrangement of layers and regions of different conductance and different conductivity types for a plurality of devices by doping with impurity forming elements, both of the major surfaces of the semiconductor wafer are provided with respective metal layers and output electrodes are applied to both of the metal layers for the plurality of devices with the output electrodes being of such a thickness and overlying such areas of the metal layers so that the thickness of the electrodes will still be sufficient for further processing after a subsequent separation of the wafer into the plurality of chips and the major surfaces of the chips after separation, are completely covered by the output electrodes. The semiconductor wafer is then separated into the intended plurality of individual chips which are then provided, if required, with a contour which reduces the field intensity. The individual chips are then etched, measured, and if required repeatedly etched and measured and, if found satisfactory, are provided with a protective layer on the exposed semiconductor surfaces.
Inventors
- 👤 Wolfgang Beerwerth
- 👤 Albrecht Geppert
- 👤 Horst Gesing
- 👤 Rigobert Schimmer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 10:07
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/102; H10D62/103; H10D62/104; H10P; H10P52/00; H10P95/00; H10W; H10W20/00; H10W20/40; H10W74/00; H10W74/10; H10W74/131; H10W76/00; H10W76/10; H10W76/12; H10W76/13; H10W76/138; H10W72/00; H10W72/071; H10W72/073; H10W72/07331; H10W72/07336; H10W72/07351; H10W72/07352; H10W72/20; H10W72/251; H10W72/252; H10W72/30; H10W72/321; H10W72/325; H10W72/351; H10W72/352; H10W72/353; H10W72/354; Y; Y10; Y10S; Y10S438/00; Y10S438/959; Y10S438/978
Claims Analysis
Total Claims: 41
Claim 1
Independent Claim
200 words
Method for producing diffused, contacted and surface passivated semiconductor chips for semiconductor devices, comprising the steps of: a. producing a given arrangement of layers and regions of different conductance and different conductivity types for a plurality of devices in a semiconductor wafer by doping with impurity forming elements; b. applying a metal layer to both of the major surfaces of the semiconductor wafer; c. applying output electrodes for the plurality of devices to both metal layers with the output electrodes having such a thickness and overlying such areas of the metal layers so that after a subsequent separation of the wafer into a plurality of chips the thickness of the electrodes will still be sufficient for further processing and the major surfaces of the individual chips are completely covered by the output electrodes; d. separating the semiconductor wafer into the intended plurality of individual contacted chips; e. etching the exposed semiconductor surfaces of the individual contacted chips; f. measuring the operating characteristics of the individual chips; g. repeating steps (e) and (f) as required until the measured chip has satisfactory operating characteristics; and h. providing the exposed semiconductor surfaces of the chips with satisfactory operating characteristics with a protective layer.
Claim 2
Dependent Claim
200 words
Method for producing diffused, contacted and surface passivated semiconductor chips for semiconductor devices, comprising the steps of: a. producing a given arrangement of layers and regions of different conductance and different conductivity types for a plurality of devices in a semiconductor wafer by doping with impurity forming elements; b. applying a metal layer to both of the major surfaces of the semiconductor wafer; c. applying output electrodes for the plurality of devices to both metal layers with the output electrodes having such a thickness and overlying such areas of the metal layers so that after a subsequent separation of the wafer into a plurality of chips the thickness of the electrodes will still be sufficient for further processing and the major surfaces of the individual chips are completely covered by the output electrodes; d. separating the semiconductor wafer into the intended plurality of individual contacted chips; e. etching the exposed semiconductor surfaces of the individual contacted chips; f. measuring the operating characteristics of the individual chips; g. repeating steps (e) and (f) as required until the measured chip has satisfactory operating characteristics; and h. providing the exposed semiconductor surfaces of the chips with satisfactory operating characteristics with a protective layer.
Claim 3
Dependent Claim
35 words
The method as defined in claim 1 further comprising: prior to said step (e), contouring the edge surfaces of the semiconductor chips to reduce the field intensity at the pn-junctions extending to the edge surfaces.
Claim 4
Dependent Claim
29 words
The method as defined in claim 1 wherein said step (c) includes covering the entire surface area of both major surfaces of the semiconductor wafer with the metal layers.
Claim 5
Dependent Claim
14 words
The method as defined in claim 1 wherein the metal layers are nickel layers.
Claim 6
Dependent Claim
15 words
The method as defined in claim 4 wherein the output electrodes are made of silver.
Claim 7
Dependent Claim
13 words
The method as defined in claim 4 wherein the output electrodes are nickel.
Claim 8
Dependent Claim
15 words
The method as defined in claim 4 wherein the output electrodes are a silver/nickel alloy.
Claim 9
Dependent Claim
40 words
The method as defined in claim 4 wherein the output electrodes are formed of a metal selected from the group consisting of tungsten, molybdenum and a nickel, cobalt, iron alloy, which metal is provided with soft solderable and etch-resistant coatings.
Claim 10
Dependent Claim
26 words
The method as defined in claim 8 wherein said step (c) includes soldering the output electrodes to the respective metal layers with an etch-resistant soft solder.
Claim 11
Dependent Claim
26 words
The method as defined in claim 1 wherein said step (c) includes soldering the output electrodes to the respective metal layers with an etch-resistant soft solder.
Claim 12
Dependent Claim
20 words
The method as defined in claim 10 wherein the soft solder has the composition Pb 90%, Ag 5%, In 5%.
Claim 13
Dependent Claim
63 words
The method as defined in claim 10 wherein said step (c) further includes prior to soldering placing a shaped body of a conductive material having a higher melting point than the solder, and which serves as a spacer, between the surface of the respective contact electrode and the metal layer, to prevent the subsequent flow of molten solder out from under the electrodes.
Claim 14
Dependent Claim
24 words
The method as defined in claim 1 wherein the applied output electrodes have a thickness which is greater than that of the semiconductor wafer.
Claim 15
Dependent Claim
30 words
The method as defined in claim 13 wherein, for a semiconductor wafer with a thickness of about 0.3 mm, the output electrodes have thicknesses of about 0.3 to 0.6 mm.
Claim 16
Dependent Claim
29 words
The method as defined in claim 13, wherein for a semiconductor wafer with a thickness of about 0.3 mm, the output electrodes have a thickness of about 0.5 mm.
Claim 17
Dependent Claim
38 words
The method as defined in claim 13 wherein the semiconductor devices to be produced are controlled rectifiers having at least anode, cathode and gate electrodes and wherein the gate electrodes have a greater thickness than the other electrodes.
Claim 18
Dependent Claim
19 words
The method as defined in claim 16 wherein the gate electrodes are 0.5 mm thicker than the other electrodes.
Claim 19
Dependent Claim
72 words
The method as defined in claim 1 wherein: said step (d) includes directing a separating medium toward one of the major surfaces of the wafer; and said step (c) includes applying oppositely disposed output electrodes for each device to the semiconductor wafer with the output electrodes on that surface of the semiconductor wafer toward which the separating medium is to be directed having a smaller diameter than the oppositely disposed output electrodes.
Claim 20
Dependent Claim
49 words
The method as defined in claim 18 wherein, with a wafer thickness of about 0.3 mm, the output electrodes on that surface of the semiconductor wafer toward which separating medium is directed have a diameter which is about 0.3 mm less than that of the oppositely disposed output electrodes.
Claim 21
Dependent Claim
29 words
The method as defined in claim 18 wherein said step (d) of separating comprises dividing the semiconductor wafer into individual contacted chips by means of a sand blasting process.
Claim 22
Dependent Claim
28 words
The method as defined in claim 18 wherein said step (d) of separating comprises dividing the semiconductor wafer into individual contacted chips by means of an etching process.
Claim 23
Dependent Claim
30 words
The method as defined in claim 18 wherein said step (c) of separating comprises dividing the semiconductor wafer by means of a sand blasting process with a subsequent etching process.
Claim 24
Dependent Claim
83 words
The method as defined in claim 18 wherein the devices to be produced are symmetrically blocking thyristors and further comprising the step of: after said step of separating the semiconductor wafer into the intended plurality of individual contacted chips removing a portion of the edge region of the semiconductor chip so that the resulting edge of the chip is perpendicular to the surfaces of output electrodes by means of a wet sand blasting process for a duration of about 30 to 180 minutes.
Claim 25
Dependent Claim
33 words
The method as defined in claim 23 wherein aluminum oxide with a grain size of 20 to 30μ mixed with an equal quantity of water is used for the wet sand blasting process.
Claim 26
Dependent Claim
60 words
The method as defined in claim 20 further comprising the steps of: prior to said step (d) of separating, attaching the contacted semiconductor wafer to a carrier plate; and improving the blocking capabilities of the contacted chips by subjecting same to an etching process after the wet sand blasting process while the chips are still attached to the carrier plate.
Claim 27
Dependent Claim
61 words
The method as defined in claim 25 wherein the etching solution used to treat the individual contacted chips after the wet sand blasting process consists of 7 parts by volume fuming nitric acid (density more than 1.51 g/cm 3 ), 4 parts by volume of a 38 to 40% hydrofluoric acid solution and 8 parts by volume of glacial acetic acid.
Claim 28
Dependent Claim
27 words
The method as defined in claim 26 wherein, the individual contacted chips are treated with the etching solution for a duration of from 2 to 10 minutes.
Claim 29
Dependent Claim
24 words
The method as defined in claim 27 wherein, the individual contacted chips are treated with the etching solution for a duration of 5 minutes.
Claim 30
Dependent Claim
26 words
The method as defined in claim 28 wherein the individual contacted chips are treated with the etching solution at a temperature of about 26° to 30°C.
Claim 31
Dependent Claim
33 words
The method as defined in claim 29 further comprising: removing the contacted chips from the carrier plate devices and thereafter subjecting the individual contacted chips to a second etching treatment in step (e).
Claim 32
Dependent Claim
55 words
The method as defined in claim 30 wherein said etching step (e) is carried out with an etching solution consisting of 2 parts by volume fuming nitric acid (density more than 1.51 g/cm 3 ), 1 part by volume of a 38 to 40% hydrofluoric acid solution and 1 part by volume glacial acetic acid.
Claim 33
Dependent Claim
29 words
The method as defined in claim 31 wherein the individual chips are treated with etching solution in said step (e) for a duration of from 30 to 90 seconds.
Claim 34
Dependent Claim
23 words
The method as defined in claim 32 wherein the individual chips are treated with the etching solution for a duration of 60 seconds.
Claim 35
Dependent Claim
40 words
The method as defined in claim 25 further comprising: removing the individual contacted chips from the carrier plate; and prior to said step (e), grinding the edges of the individual semiconductor chips to provide same with a desired edge contour.
Claim 36
Dependent Claim
44 words
The method as defined in claim 34 wherein said step of grinding comprises pressing the edge of the semiconductor chip against a tensioned wire while rotating the semiconductor chip about its axis, and simultaneously adding a grinding agent between the chip and the wire.
Claim 37
Dependent Claim
28 words
The method as defined in claim 35 wherein the grinding agent is a slurry consisting substantially of 2 liters water, 1 liter glycerine and 600 g silicon carbide.
Claim 38
Dependent Claim
17 words
The method as defined in claim 36 wherein the grinding wire is formed of steel or tungsten.
Claim 39
Dependent Claim
33 words
The method as defined in claim 1 wherein said step (e) includes etching the individual contacted chips with a final etching solution of fuming nitric acid (density more than 1.51 g/cm 3 ).
Claim 40
Dependent Claim
31 words
The method as defined in claim 38 wherein the individual chips are subjected to said final etching solution of fuming nitric acid for a duration of from 30 to 90 seconds.
Claim 41
Dependent Claim
28 words
The method as defined in claim 39 wherein the individual devices are subjected to said final etching solution of fuming nitric acid for a duration of 60 seconds.
References Cited (Backward Citations)
US2854366A
Cited
US3140527A
Cited
US3197839A
Cited
US3288662A
Cited
US3512051A
Cited
US3523223A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-06-29 | 1979-12-29 | 1980-06-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-06-29 | 1983-12-29 | 1984-06-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-06-29 | 1987-12-29 | 1988-06-29 | $7700.00 | Window Closed / Lapsed |