Patent US3555003A successfully refreshed from Google Patents.
Patent US3978408A successfully refreshed from Google Patents.
US3978408A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit arrangement for selecting a diversity channel
Assignee: Siemens AG
•
Filing: 1974-12-05
•
Granted: 1976-08-31
•
Expires: 1994-12-05
Abstract
Abstract Apparatus for selecting a diversity channel in a data processing system is described. Data from a data source are assigned a signal whose binary values change within a given test period. At the receiver, a test device produces test signals indicating parameters of the received signals, and in dependence upon the test signals one of the diversity channels is connected by a channel switch to a data sink.
Inventors
- 👤 Jutta Das Gupta
- 👤 Wernhard Markwitz
- 👤 Max Ollinger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:29
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/02
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
165 words
In a data transmission system, apparatus for selecting one of a plurality of diversity channels, comprising: receiving means for receiving data-modulated signals transmitted in each of said diversity channels, said data-modulated signals including binary data modulating signals which assume one of two binary states in time succession and wherein transitions between the two states occur within predetermined test periods, demodulating means for demodulating said received data-modulated signals and producing demodulated outputs on each of said diversity channels, test means for receiving said demodulated outputs and for producing therefrom test signals of a first type indicating the absence of binary transitions in a said demodulated output and test signals of a second type indicating the presence of distortions in a said demodulated output, quality evaluation means for producing control signals as a function of said first type test signals and said second type test signals and channel switch means for selectively connecting, responsive to said control signals, one of said diversity channels to a data sink.
Claim 2
Dependent Claim
165 words
In a data transmission system, apparatus for selecting one of a plurality of diversity channels, comprising: receiving means for receiving data-modulated signals transmitted in each of said diversity channels, said data-modulated signals including binary data modulating signals which assume one of two binary states in time succession and wherein transitions between the two states occur within predetermined test periods, demodulating means for demodulating said received data-modulated signals and producing demodulated outputs on each of said diversity channels, test means for receiving said demodulated outputs and for producing therefrom test signals of a first type indicating the absence of binary transitions in a said demodulated output and test signals of a second type indicating the presence of distortions in a said demodulated output, quality evaluation means for producing control signals as a function of said first type test signals and said second type test signals and channel switch means for selectively connecting, responsive to said control signals, one of said diversity channels to a data sink.
Claim 3
Dependent Claim
29 words
The apparatus defined in claim 1 further comprising: means in said test means for producing test signals of a third type indicating the rate of said transmitted, data-modulated signals.
Claim 4
Dependent Claim
67 words
The apparatus defined in claim 1 wherein said test means comprises: a pair of differentiators for each said diversity channel, each said pair of differentiators being connected, respectively, to one of said demodulated outputs, bistable trigger means for each said diversity channel, each said bistable trigger means being connected, respectively, to the outputs of said pair of differentiators for emitting said test signals of said first type.
Claim 5
Dependent Claim
71 words
The apparatus defined in claim 3 further comprising: synchronizing means for producing a timing signal comprising a sequence of rectangular pulses which occur during given bit patterns and having pulse durations equal to a fraction of the bit duration of said demodulated outputs and second gating means having inputs coupled to receive outputs from said pairs of differentiator stages and said timing signal for emitting therefrom said second type test signals.
Claim 6
Dependent Claim
124 words
The apparatus defined in claim 1 wherein said quality evaluation stage comprises: a plurality of counter means, one of which is assigned to each said diversity channel, each said counter means having first and second inputs coupled to receive, respectively, said test signals of said first and second types, each said counter means being constructed to respond with a greater count for said first type test signals, each said counter means including reset means operable after a counting time equal to a test period or a multiple thereof, each said counter means having outputs which represent increasingly higher counts in correspondence with the poorness of quality of the assigned diversity channel and means for producing said control signals responsive to said counter output signals.
Claim 7
Dependent Claim
53 words
The apparatus defined in claim 5 wherein said means for producing control signals comprises: first logic circuit means for producing output signals indicative of the transmission qualities of said diversity channels and second logic circuit means having inputs coupled to receive said first logic circuit means output signals for producing said control signals.
Claim 8
Dependent Claim
79 words
The apparatus defined in claim 6 wherein said first logic circuit means includes a plurality of comparators, one of which is assigned to each said diversity channel, each said comparator having inputs coupled to outputs of two of said counter means and having three outputs for emitting signals which indicate whether one of said counted values is greater than the other and first gating means responsive to said comparator outputs for emitting said first logic circuit means output signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-08-31 | 1980-03-01 | 1980-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-08-31 | 1984-03-01 | 1984-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-08-31 | 1988-03-01 | 1988-08-31 | $7700.00 | Window Closed / Lapsed |