Indirect memory addressing

Claim 1

In a system for indirectly addressing dedicated locations in a memory 34, wherein each of said dedicated locations contain a data address signal to another location in said memory, and said system includes a central processing unit (CPU) 12 for interrogating or writing into said memory and for generating indirect address signals comprising most significant bits addressed to said dedicated location and least significant bits not addressed to said dedicated location: a register means 36 connected to receive and store address signals from said dedicated locations in said memory; a switchable multiplexer means 30 for switching a normal connection from said CPU to said memory to a connection from said register means to said memory; a decoder means 50 responsive to the indirect address signal for interrupting operation of said CPU; a sequencer means 68 actuated by said decoder means ascertaining an indirect address signal for generating a series of successive timing pulses; a source of signals 42 rendered effective by a first of said timing pulses T-1 to changing the least significant bits in the indirect address signals applied to said multiplexer means to bits addressed to the dedicated location; means responsive to the signal now applied by the multiplexer means to the dedicated location in the memory and a second timing pulse T-2 for reading and applying the data address signal in said dedicated location to said register means; means responsive to a third timing pulse T-3 for triggering the register means to store the data address signal; means responsive to a subsequent timing pulse T-6 for switching the multiplexer to apply the data address stored in the register means to the memory; and means responsive to the next subsequent timing pulse T-7 for reinitiating operation of the CPU to interrogate or write into the memory location at the data address.