Method and structure for controllng carrier lifetime in semiconductor devices

Claim 2

An integrated semiconductor device in a semiconductor substrate of monocrystalline semiconductor material of a first type conductivity, regions of a second opposite type conductivity, complementary field effect transistors in the substrate and in the regions, the improvement comprising at least one region of implanted inert atoms within the device, said inert atoms selected from the group consisting of argon, krypton and xenon that reduce the gain of parasitic transistor action by reducing the minority carrier lifetime, said implanted inert atoms in said region forming substantially immobile recombination centers, said region subjected to a high temperature anneal that substantially recrystallizes any lattice damage resulting from the implantation step, the concentration of said implanted inert atoms being substantially greater than the density of any remaining lattice damage sites.

Claim 3

The device of claim 1 wherein said inert atoms are argon introduced by ion implantation.

Claim 4

The device of claim 1 wherein said region is a blanket implant region located beneath and spaced from the source and drain regions.

Claim 5

The device of claim 1 wherein said region is a plurality of planar regions in said regions of opposite conductivity located beneath and spaced from the source and drain regions.

Claim 6

The device of claim 1 wherein said region is a plurality of annular regions separating said transistors.

Claim 7

The device of claim 3 wherein said region further includes regions of inert atoms that provide lateral separation of the transistors.

Claim 8

The device of claim 1 wherein the concentration of inert atoms is in the range of 10 14 to 10 16 atoms/cm 2 .

Claim 9

The device of claim 1 wherein said first type conductivity is N, and said opposite type conductivity is P, the transistors in said regions of opposite conductivity are N-channel, and the transistors in said substrate are P-channel.

Claim 10

An integrated circuit semiconductor device in a substrate of a monocrystalline semiconductor material having a plurality of transistor elements, each provided with a collector region, a base region having a flat junction that is parallel to the top surface, and an emitter region, the improvement comprising a region of implanted inert atoms within said device in at least the collector region having a significant concentration of atoms selected from the group consisting of argon, krypton and xenon, said region of implanted inert atoms in operation reducing the minority carrier lifetime, said implanted inert atoms in said region for forming substantially immobile recombination centers, said region subjected to a high temperature anneal that substantially recyrstallizes any lattice damage resulting from the implantation step, the concentration of said implanted inert atoms being substantially greater than the density of any remaining lattice damage sites.

Claim 11

An integrated circuit semiconductor device in a substrate of a monocrystalline semiconductor material having a plurality of transistor elements, each provided with a collector region, a base region having a flat junction that is parallel to the top surface, and an emitter region, the improvement comprising a region of implanted inert atoms within said device in at least the collector region having a significant concentration of atoms selected from the group consisting of argon, krypton and xenon, said region of implanted inert atoms in operation reducing the minority carrier lifetime, said implanted inert atoms in said region for forming substantially immobile recombination centers, said region subjected to a high temperature anneal that substantially recyrstallizes any lattice damage resulting from the implantation step, the concentration of said implanted inert atoms being substantially greater than the density of any remaining lattice damage sites.

Claim 12

The device of claim 9 wherein said implanted region is a blanket implant region.

Claim 13

The device of claim 9 wherein said implanted region substantially underlies only the base region of the transistor.

Claim 14

The device of claim 9 wherein said inert atom is argon.

Claim 15

The device of claim 12 wherein the concentration of inert atoms in said implanted region is in the range of 10 14 to 10 16 atoms/cm 2 .

Claim 16

The device of claim 9 wherein said implanted region extends to the collector base junction.