FET and bipolar device and circuit process with maximum junction control

Claim 2

A semiconductor dielectrically isolated mesa junction field-effect transistor having a precisely controlled junction thickness comprising in combination: a. a first epitaxial layer of monocrystalline semiconductor material of one conductivity type; b. a second epitaxial layer of monocrystalline semiconductor material of the opposite conductivity type overlying said first layer to provide a channel layer; c. a groove circumscribing said first and second layers to provide an air isolated single crystal mesa comprising said layers, d. a first plurality of semiconductor regions having said opposite conductivity type spaced within the surface of said second layer, said first plurality providing source and drain regions; and e. a second plurality of semiconductor regions having said one conductivity type spaced within the surface of said second layer, alternately positioned between said first plurality, said second plurality providing front gate regions.

Claim 3

The transistor of claim 1 wherein said semiconductor materials is monocrystalline silicon having a crystal orientation of (100).

Claim 4

The transistor of claim 2 and further comprising at least one region of said one conductivity type disposed in and through said second layer for providing electrical contact to said first layer, thereby providing a back gate layer.

Claim 5

The transistor of claim 3 wherein said source regions are electrically common, said drain regions are electrically common.

Claim 6

A semiconductor dielectrically isolated mesa junction field effect transistor having a precisely controlled junction thickness comprising in combination: a. a substrate to provide support; b. a first layer of monocrystalline semiconductor material of one conductivity type; c. a second layer of epitaxial monocrystalline semiconductor material of the opposite conductivity type overlying said first layer to provide a channel layer; d. an isolation layer between said substrate and said first layer; e. a dielectrically filled groove circumscribing said first and second layers to provide a single crystal mesa comprising said layers; f. a first plurality of semiconductor regions having said opposite conductivity type spaced within the surface of said second layer, said first plurality providing source and drain regions; and g. a second plurality of semiconductor regions having said one conductivity type spaced within the surface of said second layer, alternately positioned between said first plurality, said second plurality providing front gate regions.

Claim 7

A semiconductor dielectrically isolated mesa junction field effect transistor having a precisely controlled junction thickness comprising in combination: a. a substrate to provide support; b. a first layer of monocrystalline semiconductor material of one conductivity type; c. a second layer of epitaxial monocrystalline semiconductor material of the opposite conductivity type overlying said first layer to provide a channel layer; d. an isolation layer between said substrate and said first layer; e. a dielectrically filled groove circumscribing said first and second layers to provide a single crystal mesa comprising said layers; f. a first plurality of semiconductor regions having said opposite conductivity type spaced within the surface of said second layer, said first plurality providing source and drain regions; and g. a second plurality of semiconductor regions having said one conductivity type spaced within the surface of said second layer, alternately positioned between said first plurality, said second plurality providing front gate regions.

Claim 8

The semiconductor transistor according to claim 5 wherein said dielectric in the groove is air.

Claim 9

The transistor of claim 5 and including a plurality of other like transistors disposed in other like mesas, each dielectrically isolated and disposed on said isolation layer.