Apparatus for correlating two time series

Claim 2

Electronic apparatus for correlating two time series of sampled quantities comprising: sign bit series means having an input for receiving a first of said two time series of sampled quantities and having an output for providing a sign bit representation of said first series, said representation including addresses of zero crossings of said first series and indications of direction of each zero crossing; data input means having first input for receiving a second of said two time series of sampled quantities, a second input coupled to the sign bit series means output for receiving zero crossing addresses, and an output for providing sampled quantities of said second series which correspond to zero crossings of said first series; sign modifying means having a first input coupled to said data input means for receiving the sign portion of sampled quantities of said second series, a second input coupled to the sign bit series means for receiving zero crossing direction indications, and an output for providing a modified sign portion; and summing means coupled to said data input means' output and to said sign modifying means' output for algebraically summing sampled quantities of said second series which correspond to zero crossings of said first time series.

Claim 3

Electronic apparatus according to claim 1 wherein said data input means is a random access memory having one storage location for each quantity of the second series of sampled quantities.

Claim 4

Electronic apparatus according to claim 1 wherein said data input means and said summing means include: data storage means having an input for receiving and storing one sample of the second time series at a time, a first output for providing the stored sampled quantity, and a second output for providing an indication of receipt of a sample; a sample counter having an input coupled to the second output of the data storage means and an output for providing an indication of the total number of samples receiving by the data storage means; an address subtractor having inputs coupled to the output of the sample counter and to the output of the sign bit series means and an output for providing the difference between the sample counter output and the sign bit series means' zero crossing address output; a memory having an address input coupled to the address subtractor output and having an output for reading and writing information from and into an addressed memory location; and an adder having a first input coupled to the data storage means output, a second input coupled to the sign modifying means output, and a third input coupled to the memory output for algebraically adding the sample quantity received on its first and second inputs to a quantity received from the memory and for coupling the sum back to the memory.

Claim 5

Electronic apparatus according to claim 1 further including multiplier means coupled to said data input means and to said summing means for doubling the magnitude of each value of said second series which is coupled to the output of the data input means, except for the first and last values.

Claim 6

Electronic apparatus according to claim 1 further including integrator means coupled to said summing means for generating an integral of a sequence of outputs of said summing means.

Claim 7

Electronic apparatus according to claim 5 wherein said integrator means is a strip chart recorder which generates a visual record corresponding to the integral of an input signal.

Claim 10

A method according to claim 7 further including the steps of: outputting the sample numbers and directions of zero crossigns of said first series from said zero crossing detector to a phase shifter for adding one unit to each address of zero crossings of said first series; introducing said second series to the sample selector for, in response to the outputs of said phase shifter, selecting sampled values of said second series which correspond to phase-shifted zero crossings of said first series; introducing the selected values of said second series into the sign-modifying means for, in response to the outputs of said phase shifter, changing the sign of the selected values of the second series which correspond to phase-shifted, positive-going zero crossings of said first series; and outputting said selected and sign-modified values of said second series to the summer for algebraically summing said selected and sign-modified values of said second series.

Claim 11

A method according to claim 8 further including the step of sequentially introducing the outputs of the summer into an integrator for generating the integral of said outputs.