Abstract An electronic timepiece uses a dynamic type shift register, as a time count circuit, which has a plurality of memory sections corresponding to an equal number of time count units and a cycle number memory section arranged such that it is preceded by said plurality of memory sections. An adder and shift memory unit are serially connected to the shift register to provide a shift circulation circuit and the shift circulation is effected by an oscillation signal from a reference oscillator. The adder adds [1] to the contents of the cycle number memory section for each data shift cycle of the shift register. Each time the count value of the cycle number memory section reaches a predetermined cycle number, the count value of a smallest time unit is counted one step. In this way, a carry is propagated to the subsequent large time unit memory sections according to the data shift circulation cycle of the shift register. A memory circuit is also provided which preliminarily stores a correction value corresponding to an error occuring between the oscillation frequency of the reference oscillator as generated per unit time and the standard oscillation frequency which drives the shift circulation circuit. Upon receipt of a correction timing signal the memory circuit has its correction value substracted at a rate of one circulation cycle per minute, thereby to correct such an error. The correction value indicates a total number of subtractive circulation cycle per hour.
Inventors
👤 Toshio Kashio
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-11-01 06:55
CPC Classifications
G; G04; G04G; G04G3/00; G04G3/02; G04G3/025
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
234 words
An electronic timepiece comprising a reference oscillator; shift memory means adapted to be controlled in accordance with an oscillation signal from the reference oscillator and having a plurality of time count memory sections corresponding to an equal number of time count units and a cycle number memory section arranged such that it is preceded by the plurality of time count memory sections, said shift memory means being such that memory data can be sequentially shifted as a carry from the cycle number memory section toward the successive time count memory sections; means for adding to the contents of the cycle number memory section for each data shift cycle of the memory shift means; means for permitting the contents of a smallest time unit memory section of said memory sections to be counted one step when the count value of said cycle number memory reaction reaches a predetermined cycle number and for permitting a carry to the subsequent large time unit memory sections; write means for writing a correction value x corresponding to an error per a predetermined unit time as induced between a standard oscillation frequency and an oscillation frequency of said reference oscillator; setting means for setting x number of correction timings into which said predetermined unit time is divided; and means for correcting said predetermined cycle number counted in the cycle number memory section for each timing set by said setting means.
Claim 2
Dependent Claim
234 words
An electronic timepiece comprising a reference oscillator; shift memory means adapted to be controlled in accordance with an oscillation signal from the reference oscillator and having a plurality of time count memory sections corresponding to an equal number of time count units and a cycle number memory section arranged such that it is preceded by the plurality of time count memory sections, said shift memory means being such that memory data can be sequentially shifted as a carry from the cycle number memory section toward the successive time count memory sections; means for adding to the contents of the cycle number memory section for each data shift cycle of the memory shift means; means for permitting the contents of a smallest time unit memory section of said memory sections to be counted one step when the count value of said cycle number memory reaction reaches a predetermined cycle number and for permitting a carry to the subsequent large time unit memory sections; write means for writing a correction value x corresponding to an error per a predetermined unit time as induced between a standard oscillation frequency and an oscillation frequency of said reference oscillator; setting means for setting x number of correction timings into which said predetermined unit time is divided; and means for correcting said predetermined cycle number counted in the cycle number memory section for each timing set by said setting means.
Claim 3
Dependent Claim
143 words
The electronic timepiece according to claim 1, in which said write means is set as first and second correction value memory sections in a predetermined area of said shift memory means, and comprises means for writing said correction value x in either one of said first and second correction value memory sections, means for designating a correction value stored in one of said first and second correction value memory sections for each predetermined unit time, means for substracting [1] from the contents in said correction valuestored memory section for each of said x number of timings until said correction value x becomes zero, and adding [1] to the other correction value memory section, and means for correcting said predetermined value in said cycle number memory section each time such subtraction and addition are effected with respect to said one and other memory sections.
Claim 4
Dependent Claim
82 words
The electronic timepiece according to claim 1, in which said write means is adapted to write data in a different memory means from said shift memory means and comprises means for transmitting the correction value x from said different memory means to a time count circuit for each unit time, means for subtracting the correction value x transferred to said time count circuit, and means for correcting the cycle number as counted at the cycle number memory section for each correction timing.
Claim 5
Dependent Claim
20 words
The electronic timepiece according to claim 1, in which said shift memory means is constructed of a dynamic shift register.
Claim 6
Dependent Claim
20 words
The electronic timepiece according to claim 2, in which said shift memory means is constructed of a dynamic shift register.
Claim 7
Dependent Claim
20 words
The electronic timepiece according to claim 3, in which said shift memory means is constructed of a dynamic shift register.