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US4142111A
Expired / Lapsed
US
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One-transistor fully static semiconductor memory cell
Assignee: Texas Instruments Inc
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Filing: 1977-01-27
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Granted: 1979-02-27
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Expires: 1997-01-27
Abstract
Abstract A cell for a semiconductor memory of the static type employs only one conventional MOS transistor, along with a field implanted resistance and a vertical P-channel junction-type field effect transistor. These elements, along with a resistor element which may be another field implanted resistance or a polysilicon implanted resistance, provide a circuit which is stable with either a "1" or "0" stored. No clock or other refresh circuitry is needed.
Inventors
- 👤 David J. McElroy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:48
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/39; G11C11/40; G11C11/41; G11C11/412; H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
175 words
A semiconductor integrated circuit comprising an MOS transistor having a source-drain path and a gate, the source-drain path of the MOS transistor being connected between a first node and a source of logic voltages, the gate of the MOS transistor being connected to a different source of logic voltages, an implanted field effect resistor having a current path, the current path of the field effect resistor being connected between the first node and a second node, impedance means connecting the second node to a voltage supply, a vertically oriented field effect transistor having a source-drain path and a gate, the gate of the field effect transistor being connected to the second node, means connecting the first node through the source-drain path of the field effect transistor to a reference potential, the field effect resistor and the field effect transistor both exhibiting a low impedance state when the voltage on the first and second nodes is relatively low and exhibiting a high impedance state when the voltage on the first and second nodes is relatively high.
Claim 2
Dependent Claim
175 words
A semiconductor integrated circuit comprising an MOS transistor having a source-drain path and a gate, the source-drain path of the MOS transistor being connected between a first node and a source of logic voltages, the gate of the MOS transistor being connected to a different source of logic voltages, an implanted field effect resistor having a current path, the current path of the field effect resistor being connected between the first node and a second node, impedance means connecting the second node to a voltage supply, a vertically oriented field effect transistor having a source-drain path and a gate, the gate of the field effect transistor being connected to the second node, means connecting the first node through the source-drain path of the field effect transistor to a reference potential, the field effect resistor and the field effect transistor both exhibiting a low impedance state when the voltage on the first and second nodes is relatively low and exhibiting a high impedance state when the voltage on the first and second nodes is relatively high.
Claim 3
Dependent Claim
21 words
A circuit according to claim 1 wherein the impedance means is an ion implanted polycrystalline silicon resistor overlying thick field oxide.
Claim 4
Dependent Claim
28 words
A circuit according to claim 2 wherein the field effect resistor is a region within the semiconductor material formed by ion implant and having a low impurity concentration.
Claim 5
Dependent Claim
22 words
A circuit according to claim 3 wherein the region which forms the impedance element is buried beneath a thick thermal oxide layer.
Claim 6
Dependent Claim
26 words
A circuit according to claim 1 wherein the impedance means is a second field effect resistor formed by ion implant beneath a thick field effect layer.
Claim 7
Dependent Claim
27 words
A circuit according to claim 5 wherein the field effect transistor is of the P-channel p-n junction type and the gate region is an N+ arcuate region.
Claim 8
Dependent Claim
51 words
A circuit according to claim 1 wherein the source of logic voltages is a bit line in a memory array, the different source of logic voltages is an address line in the memory array, and the first node is a storage node capable of sustaining a logic "1" or logic "0".
Claim 9
Dependent Claim
100 words
A storage cell comprising an address line, a data line, first and second storage nodes, a first controlled switching device having a current path connecting the data line to one of the first and second storage nodes and being controlled by the address line, a voltage supply, impedance means connecting the second storage node to the voltage supply, voltage-controlled resistance means connecting the first storage node to the second storage node, the second storage node being connected to the control element of a second controlled switching device, the second controlled switching device connecting the first storage node to reference potential.
Claim 10
Dependent Claim
100 words
A storage cell comprising an address line, a data line, first and second storage nodes, a first controlled switching device having a current path connecting the data line to one of the first and second storage nodes and being controlled by the address line, a voltage supply, impedance means connecting the second storage node to the voltage supply, voltage-controlled resistance means connecting the first storage node to the second storage node, the second storage node being connected to the control element of a second controlled switching device, the second controlled switching device connecting the first storage node to reference potential.
Claim 11
Dependent Claim
21 words
A storage cell according to claim 8 wherein the resistance means is responsive to the voltage on the first storage node.
Claim 12
Dependent Claim
72 words
A storage cell according to claim 9 wherein the resistance means has a first terminal connected to the first storage node and a second terminal connected to the second storage node, wherein means are provided for applying voltage at said terminals, and wherein the resistance means exhibits a large change in resistance when the voltage at said second terminal changes from near reference potential to near the value of the voltage supply.
Claim 13
Dependent Claim
22 words
A storage cell according to claim 10 wherein the second controlled switching device is a vertically oriented junction type field effect transistor.
Claim 14
Dependent Claim
40 words
A storage cell according to claim 11 wherein the second controlled switching device exhibits a large change in impedance when the voltage on the second storage node changes from near reference potential to near the value of the supply voltage.
Claim 15
Dependent Claim
28 words
A storage cell according to claim 12 wherein the cell is stable with either a logic "1" or a logic "0" on the first and second storage nodes.
Claim 16
Dependent Claim
40 words
A storage cell according to claim 13 wherein the first controlled switching device is an N-channel MOS transistor, the resistance means resembles an N-channel junction field effect transistor, and the second controlled switching device is a P-channel field effect transistor.
Claim 17
Dependent Claim
22 words
A storage cell according to claim 14 wherein the resistance means comprises an ion-implanted region beneath a thick, thermally-grown field oxide layer.
Claim 18
Dependent Claim
23 words
A storage cell according to claim 15 wherein the impedance means is an ion-implanted polycrystalline silicon strip overlying a thick field oxide layer.
Claim 19
Dependent Claim
26 words
A storage cell according to claim 15 wherein the impedance means is an ion-implanted region beneath a thick field oxide layer and resembles the resistance means.
Claim 20
Dependent Claim
124 words
A storage cell comprising an address line, a data line, first and second storage nodes, a first controlled switching device having a current path connecting the data line to one of the first and second storage nodes and being controlled by the address line wherein the first controlled switching device is an MOS transistor, a voltage supply, impedance means connecting the second storage node to the voltage supply, voltage-controlled resistance means connecting the first storage node to the second storage node, the second storage node being connected to the control element of a second controlled switching device, wherein the second controlled switching device is a vertically oriented junction-type field effect transistor, the second controlled switching device connecting the first storage node to reference potential.
Claim 21
Dependent Claim
124 words
A storage cell comprising an address line, a data line, first and second storage nodes, a first controlled switching device having a current path connecting the data line to one of the first and second storage nodes and being controlled by the address line wherein the first controlled switching device is an MOS transistor, a voltage supply, impedance means connecting the second storage node to the voltage supply, voltage-controlled resistance means connecting the first storage node to the second storage node, the second storage node being connected to the control element of a second controlled switching device, wherein the second controlled switching device is a vertically oriented junction-type field effect transistor, the second controlled switching device connecting the first storage node to reference potential.
Claim 22
Dependent Claim
135 words
A storage cell comprising an address line wherein the cell is within a semiconductor integrated circuit, a data line, first and second storage nodes, a first controlled switching device having a current path connecting the data line to one of the first and second storage nodes and being controlled by the address line, a voltage supply, impedance means connecting the second storage node to the voltage supply, voltage-controlled resistance means connecting the first storage node to the second storage node, wherein the resistance means is formed by an elongated ion implanted region in the semiconductor material of low net impurity concentration buried beneath thick field oxide, the second storage node being connected to the control element of a second controlled switching device, the second controlled switching device connecting the first storage node to reference potential.
Claim 23
Dependent Claim
135 words
A storage cell comprising an address line wherein the cell is within a semiconductor integrated circuit, a data line, first and second storage nodes, a first controlled switching device having a current path connecting the data line to one of the first and second storage nodes and being controlled by the address line, a voltage supply, impedance means connecting the second storage node to the voltage supply, voltage-controlled resistance means connecting the first storage node to the second storage node, wherein the resistance means is formed by an elongated ion implanted region in the semiconductor material of low net impurity concentration buried beneath thick field oxide, the second storage node being connected to the control element of a second controlled switching device, the second controlled switching device connecting the first storage node to reference potential.
References Cited (Backward Citations)
US4000427A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-02-26 | 1982-08-28 | 1983-02-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-02-26 | 1986-08-28 | 1987-02-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-02-26 | 1990-08-28 | 1991-02-27 | $7700.00 | Window Closed / Lapsed |