Integrated circuit device

Claim 1

An integrated circuit device having an input terminal and formed in a semiconductor substrate of a first conductivity type comprising: a first semiconductor section in said semiconductor substrate in which there is formed a first well region having a second conductivity type opposite to said first conductivity type, complementary MOS elements formed in said first semiconductor section, one inside and one outside said first well region, said MOS elements each having a gate; a second semiconductor section in said semiconductor substrate physically separated from said first semiconductor section, in which there is formed a second well region having said second conductivity type; a first region of said first conductivity type located in said second well region to form a first protective diode between said first region and said second well region and said first region being coupled to said gates of said MOS elements; said second semiconductor section further including a second region of said second conductivity type formed in said substrate and forming a protective input resistance between first and second portions of said second region, said first portion connected to said input terminal and said second portion connected to said gates of said MOS elements and said second region further forming additional protective diodes between said second region and said second semiconductor section, said second region and said second well region both spaced sufficiently wide apart in said second semiconductor section from each other and from said first semiconductor section to prevent the occurrence of a latch-up phenomenon due to the action of lateral parasitic transistors between said first and second semiconductor sections.