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Method for providing low cost wafers for use as substrates for integrated circuits

Assignee: Unisys Corp
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Filing: 1977-12-27
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Granted: 1979-04-03
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Expires: 1997-12-27
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Abstract

Abstract The method of manufacture of the present invention provides a wafer that is better than a bulk monocrystalline silicon wafer and equivalent to silicon on sapphire (SOS) wafers for use as substrates for integrated circuits. The method comprises taking an inexpensive slab of silicon having <111> crystal orientation and by low pressure CVD, high pressure CVD, or plasma deposition techniques depositing a polycrystalline layer of sapphire on the <111> silicon base. The polycrystalline layer of sapphire is then annealed at an elevated temperature to form a monocrystalline layer having a <1101> orientation. A single crystalline layer of silicon having <111> crystal orientation is then epitaxially grown on the sapphire. The resultant multilayer wafer is equivalent in function and reliability to a silicon on sapphire wafer without the commensurate cost.

Inventors

  • 👤 Lilburn H. Garrison
  • 👤 Anant D. Dixit

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 12:43
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/692; H10P14/6938; H10P14/6939; H10P14/69391; H10P14/20; H10P14/24; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/2926; H10P14/32; H10P14/3202; H10P14/3238; H10P14/3258; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10P14/3466; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/65; H10P14/6516; H10P14/6544; Y; Y10; Y10S; Y10S117/00; Y10S117/901; Y10S117/902; Y10S148/00; Y10S148/072; Y10S148/135; Y10S438/00; Y10S438/967

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 84 words
A method for manufacturing wafers for use as substrates for integrated circuits, which wafers have a minimum of crystal defects, said method comprising: depositing a polycrystalline layer of pure sapphire upon a crystalline body having <111> orientation; annealing the polycrystalline layer of pure sapphire sufficiently to form a monocrystalline layer of pure sapphire, said monocrystalline sapphire layer having <1101> orientation; and depositing an epitactic monocrystalline layer of silicon upon the layer of monocrystalline pure sapphire, said epitactic monocrystalline silicon layer having a <111> orientation.
Claim 2
Independent Claim 84 words
A method for manufacturing wafers for use as substrates for integrated circuits, which wafers have a minimum of crystal defects, said method comprising: depositing a polycrystalline layer of pure sapphire upon a crystalline body having <111> orientation; annealing the polycrystalline layer of pure sapphire sufficiently to form a monocrystalline layer of pure sapphire, said monocrystalline sapphire layer having <1101> orientation; and depositing an epitactic monocrystalline layer of silicon upon the layer of monocrystalline pure sapphire, said epitactic monocrystalline silicon layer having a <111> orientation.
Claim 3
Dependent Claim 18 words
The method of claim 1 wherein the layer of sapphire is deposited to a thickness of 1 micron.
Claim 4
Dependent Claim 24 words
The method of claim 2 wherein the layer of silicon deposited on the layer of sapphire is deposited to a thickness of 2 microns.
Claim 5
Dependent Claim 28 words
The method of claim 1 wherein the step of depositing sapphire upon a crystalline body having <111> orientation is accomplished by using a CVD high gas flow reactor.
Claim 6
Dependent Claim 25 words
The method of claim 1 wherein the step of depositing sapphire upon a crystalline body having <111> orientation is accomplished by using a plasma reactor.
Claim 7
Dependent Claim 26 words
The method of claim 1 wherein the step of depositing sapphire upon a crystalline body having <111> orientation is accomplished by using a low pressure reactor.
Claim 8
Dependent Claim 165 words
The method of claim 1 wherein the step of depositing sapphire upon a crystalline body having <111> orientation, comprises: placing the <111> crystalline body in a controlled atmosphere environment having a pressure range of 0.5-0.9 torr; heating the <111> crystalline body within said controlled environment to a temperature within the range 250°-350° C., inclusive; flowing an inert carrier gas, such as hydrogen, through said controlled environment at a rate of approximately 600 cc/min.; and flowing trimethyl aluminum through said controlled environment at a rate within the range 40-80 cc/min., inclusive, and wherein the step of annealing comprises: placing the <111> crystalline body with the polycrystalline layer of sapphire deposited therein in a controlled atmosphere environment of inert gas, such as nitrogen; heating the environment to a temperature within the range 1100°-1300° C., inclusive; and leaving the <111> crystalline body with the polycrystalline layer of sapphire therein in the heated environment from 4 to 8 hours, until the polycrystalline layer is converted to a monocrystalline layer.

References Cited (Backward Citations)

US3476617A Cited
US3655439A Cited
US3796597A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1982-04-02 1982-10-02 1983-04-03 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1986-04-02 1986-10-02 1987-04-03 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1990-04-02 1990-10-02 1991-04-03 $7700.00 Window Closed / Lapsed

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