Method and apparatus for detection of phase difference between two electrical signals

Claim 2

In a phase comparator for comparing the phase difference between two trains of binary input signals by means of the setting of a bistable device by one of the input signals and the clearing of the bistable device by the other of the input signals wherein the output signal from the bistable device is a measure of the phase difference, the method of controllably inverting the polarity of one of the input signals comprising the steps of generating a first binary pulse train which is in synchronism with a particular characteristic of one of the trains of binary input signals, generating a second binary pulse train which is in synchronism with a particular characteristic of the other of the trains of binary input signals, the durations of the pulses in said pulse trains being fixed and independent of the frequencies of the trains of binary input signals, detecting the coincidence of one of the signal levels in the pulse trains, and whenever such coincidence is detected, changing the present polarity of one of the trains of binary input signals to the opposite polarity before the transmission thereof to the bistable device.

Claim 3

The method according to claim 1 wherein said particular characteristic is the occurrence of a pulse flank in a binary input signal.

Claim 4

The method according to claim 2 wherein said pulse flank has a particular polarity.

Claim 5

Apparatus for generating a signal whose instantaneous amplitude is a measure of the phase difference between two trains of binary input signals comprising: a bistable means having first and second inputs and an output for emitting a signal having a first level upon receipt of a signal at the first input and a signal having a second level upon receipt of a sight at the second input; a low-pass filter means connected to the output of said bistable means; controlled inverter means having a signal input, a signal output and a control input for inverting the phase of a signal received at the signal input when a control signal is present at the control input, said signal input being adapted to receive one of the two trains of binary input signals; first and second pulse generator means, each of said pulse generator means having an input and output means for generating in parallel a first pulse signal of a first width and a second pulse signal of a second and greater width for each pulse signal received at the input, the input of said first pulse generator means being connected to the output of said controlled inverter means, the input of said second pulse generator means being adapted to receive the other of the two trains of binary input signals, the output means of said first pulse generator means including means for transmitting the first pulse signals to the first input of said bistable means, the output means of said second pulse generator means including means for transmitting the first pulse signals to the second input of said bistable means, and the output means of each of said pulse generating means including means for emitting the second pulse signals; coincidence means including input means for receiving the second pulse signals from said first and second pulse generating means and an output means for emitting a trigger pulse whenever there is a coincidence between a second pulse signal received from said first pulse generating means and a second pulse signal received from said first pulse generating means; and control means responsive to the receipt of the trigger pulses for transmitting control signals to the control input of said controlled inverter means.

Claim 6

Apparatus for generating a signal whose instantaneous amplitude is a measure of the phase difference between two trains of binary input signals comprising: a bistable means having first and second inputs and an output for emitting a signal having a first level upon receipt of a signal at the first input and a signal having a second level upon receipt of a sight at the second input; a low-pass filter means connected to the output of said bistable means; controlled inverter means having a signal input, a signal output and a control input for inverting the phase of a signal received at the signal input when a control signal is present at the control input, said signal input being adapted to receive one of the two trains of binary input signals; first and second pulse generator means, each of said pulse generator means having an input and output means for generating in parallel a first pulse signal of a first width and a second pulse signal of a second and greater width for each pulse signal received at the input, the input of said first pulse generator means being connected to the output of said controlled inverter means, the input of said second pulse generator means being adapted to receive the other of the two trains of binary input signals, the output means of said first pulse generator means including means for transmitting the first pulse signals to the first input of said bistable means, the output means of said second pulse generator means including means for transmitting the first pulse signals to the second input of said bistable means, and the output means of each of said pulse generating means including means for emitting the second pulse signals; coincidence means including input means for receiving the second pulse signals from said first and second pulse generating means and an output means for emitting a trigger pulse whenever there is a coincidence between a second pulse signal received from said first pulse generating means and a second pulse signal received from said first pulse generating means; and control means responsive to the receipt of the trigger pulses for transmitting control signals to the control input of said controlled inverter means.

Claim 7

The apparatus of claim 4 wherein said control means comprises a single stage binary counter means having an input for receiving the trigger pulses and an output which switches between two signal levels in response to the receipt of a trigger pulse at the input.

Claim 8

The apparatus of claim 5 wherein said coincidence means is an OR-circuit and said second pulses are negative-going pulses.

Claim 9

The apparatus of claim 5 wherein said coincidence means is an AND-circuit and said second pulses are positive-going pulses.