Patent US4159480A successfully refreshed from Google Patents.
US4159480A
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Method of inserting an address signal in a video signal
Assignee: Sony Corp
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Filing: 1977-10-25
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Granted: 1979-06-26
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Expires: 1997-10-25
Abstract
Abstract Method and apparatus for inserting an address signal in a video signal by compressing the time code signal including synchronizing bits inserted at every predetermined bit and cyclic redundancy check code and then inserting the compressed time code signal into at least one horizontal line period within a vertical blanking period of the video signal. The invention allows the time code signals to be reconstructed where the record medium is stopped or transported at very low speeds.
Inventors
- 👤 Katsuichi Tachi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 08:29
CPC Classifications
H; H04; H04N; H04N7/00; H04N7/08; H04N7/087; H04N7/088; H04N7/0881; G; G11; G11B; G11B27/00; G11B27/02; G11B27/022; G11B27/024; G11B27/10; G11B27/19; G11B27/28; G11B27/30; G11B27/3027; G11B27/3036; G11B27/3054; G11B27/32; G11B27/322; G11B27/323; G11B2220/00; G11B2220/90; G11B27/34
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
78 words
A method of inserting an address signal in a video signal comprising the steps of: (a) providing the address signal having a plurality of time code bits corresponding to the video signal recorded on one track followed by an error check code signal; (b) selecting at least one predetermined horizontal line period within a vertical blanking period from each field or frame of said video signal; and (c) inserting said address signal in said selected one horizontal line.
Claim 2
Independent Claim
78 words
A method of inserting an address signal in a video signal comprising the steps of: (a) providing the address signal having a plurality of time code bits corresponding to the video signal recorded on one track followed by an error check code signal; (b) selecting at least one predetermined horizontal line period within a vertical blanking period from each field or frame of said video signal; and (c) inserting said address signal in said selected one horizontal line.
Claim 3
Dependent Claim
18 words
A method according to claim 1, in which said error check code is a cyclic redundancy check code.
Claim 4
Dependent Claim
50 words
A method according to claim 1, wherein said video signal includes a color subcarrier signal having a selected frequency and in which a bit frequency of said address signal is selected at 1/N of said selected frequency of said color subcarrier signal, wherein N is an integer more than 1.
Claim 5
Dependent Claim
40 words
A method according to claim 1, wherein said video signal includes a color subcarrier signal having a selected frequency and in which a bit frequency of said address signal is 1/2 of said selected frequency of the color subcarrier signal.
Claim 6
Dependent Claim
18 words
A method according to claim 1, in which said address signal includes synchronizing bits at every predetermined bits.
Claim 7
Independent Claim
76 words
A method of inserting an address signal in a video signal comprising the steps of: (a) providing the address signal having a plurality of time code bits corresponding to one field of the video signal followed by an error check code signal; (b) selecting at least one predetermined horizontal line period within a vertical blanking period from each field or frame of said video signal; (c) inserting said address signal in said selected one horizontal line.
Claim 8
Independent Claim
76 words
A method of inserting an address signal in a video signal comprising the steps of: (a) providing the address signal having a plurality of time code bits corresponding to one field of the video signal followed by an error check code signal; (b) selecting at least one predetermined horizontal line period within a vertical blanking period from each field or frame of said video signal; (c) inserting said address signal in said selected one horizontal line.
Claim 9
Dependent Claim
16 words
A method according to claim 6, in which said address signal includes a field identification bits.
Claim 10
Independent Claim
76 words
A method of inserting an address signal in a video signal comprising the steps of: (a) providing the address signal having a plurality of time code bits corresponding to one frame of the video signal followed by an error check code signal; (b) selecting at least one predetermined horizontal line period within a vertical blanking period from each field or frame of said video signal; (c) inserting said address signal in said selected one horizontal line.
Claim 11
Independent Claim
76 words
A method of inserting an address signal in a video signal comprising the steps of: (a) providing the address signal having a plurality of time code bits corresponding to one frame of the video signal followed by an error check code signal; (b) selecting at least one predetermined horizontal line period within a vertical blanking period from each field or frame of said video signal; (c) inserting said address signal in said selected one horizontal line.
Claim 12
Independent Claim
95 words
An apparatus for producing a video signal with an address signal therein, comprising: (a) means for providing the address signal corresponding to one field or frame of the video signal, said address signal consisting of a plurality of time code bits; (b) means for providing a cyclic redundancy check code signal for the address signal; (c) means for selecting at least one predetermined horizontal line period within a vertical blanking period of each field or frame of said video signal; and (d) means for inserting said address signal in said selected one horizontal line period.
Claim 13
Independent Claim
95 words
An apparatus for producing a video signal with an address signal therein, comprising: (a) means for providing the address signal corresponding to one field or frame of the video signal, said address signal consisting of a plurality of time code bits; (b) means for providing a cyclic redundancy check code signal for the address signal; (c) means for selecting at least one predetermined horizontal line period within a vertical blanking period of each field or frame of said video signal; and (d) means for inserting said address signal in said selected one horizontal line period.
Claim 14
Dependent Claim
26 words
An apparatus according to claim 9, further comprising means for providing synchronizing bits which is inserted into said address code at every predetermined number of bits.
Claim 15
Independent Claim
106 words
An apparatus for producing a video signal with an address signal therein, comprising: (a) means for producing the address signal corresponding to one field or frame of the video signal, said address signal consisting of a plurality of time code bits; (b) means for encoding the address code into an address signal; (c) means for providing a cyclic redundancy check code signal for the address signal; (d) means for selecting at least one predetermined horizontal line period within a vertical blanking period of each field or frame of said video signal; and (e) means for inserting said address signal in said selected one horizontal line period.
Claim 16
Independent Claim
106 words
An apparatus for producing a video signal with an address signal therein, comprising: (a) means for producing the address signal corresponding to one field or frame of the video signal, said address signal consisting of a plurality of time code bits; (b) means for encoding the address code into an address signal; (c) means for providing a cyclic redundancy check code signal for the address signal; (d) means for selecting at least one predetermined horizontal line period within a vertical blanking period of each field or frame of said video signal; and (e) means for inserting said address signal in said selected one horizontal line period.
Claim 17
Independent Claim
88 words
An apparatus for reproducing an address signal from a video signal, comprising: (a) means for receiving the video signal including the address signal having a plurality of time code bits corresponding to one field or frame of the video signal and a cyclic redundancy check code; (b) means for separating the address signal from the video signal; (c) means for storing the time code bits; (d) means for checking the address signal; and (e) means for generating a read-out pulse based on the output of said checking means.
Claim 18
Independent Claim
88 words
An apparatus for reproducing an address signal from a video signal, comprising: (a) means for receiving the video signal including the address signal having a plurality of time code bits corresponding to one field or frame of the video signal and a cyclic redundancy check code; (b) means for separating the address signal from the video signal; (c) means for storing the time code bits; (d) means for checking the address signal; and (e) means for generating a read-out pulse based on the output of said checking means.
Claim 19
Dependent Claim
22 words
An apparatus as claimed in claim 12, wherein said address signal further includes synchronizing bits inserted at every predetermined number of bits.
Claim 20
Dependent Claim
20 words
An apparatus as claimed in claim 13, further comprising means for correcting time base error based on the synchronizing bits.
References Cited (Backward Citations)
US3890638A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-06-25 | 1982-12-25 | 1983-06-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-06-25 | 1986-12-25 | 1987-06-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-06-25 | 1990-12-25 | 1991-06-26 | $7700.00 | Window Closed / Lapsed |