US4198608A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Glitch detector and trap
Assignee: McDonnell Douglas Corp
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Filing: 1978-07-05
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Granted: 1980-04-15
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Expires: 1998-07-05
Abstract
Abstract A glitch detector and trap circuit is disclosed for removing a glitch generated by a digital-to-analog (D/A) converter due to an error in one or more bits of the input digital signal. The analog output signal is delayed by one sample period. The converter output signal is then subtracted from the delayed converter output signal. This difference signal is passed through a full-wave precision rectifier. Thereafter, the notified signal is clipped at a predetermined trigger level so that a glitch will cause an output pulse. The output pulse caused by a glitch is used to operate a monostable circuit. The monostable circuit in turn, is utilized to change a track and store amplifier from its track mode to the store mode. In this manner, the track and store amplifier will not pass the glitch, but will remain at its previous setting. A rise-time delay circuit is interposed ahead of the track and store amplifier so that it will not respond instantaneously to the next sample pulse before its store mode is initiated.
Inventors
- 👤 William Comley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:35
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/06; H03M1/08; H03M1/0863; H03M1/0872
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
251 words
A circuit for substantially removing the undesirable effects of a glitch caused by an error in at least one bit of a digital signal applied to a digital-to-analog converter, the analog signal in turn being utilized for controlling a machine, said circuit comprising: a source of digital signals which may include an error in at least one bit; an analog-to-digital converter coupled to said source for impressing on said converter digital signals, said converter generating output pulses, each having a duration of one sample period; a track and store amplifier coupled to said converter, said track and store amplifier including a switch, which when actuated will convert the track mode of said amplifier into the store mode; means coupled to said converter for delaying the converter output signal by one sample period; means for subtracting the output of said converter from the output of said means for delaying the converter output signal and coupled to said converter and to said means for delaying; a full-wave rectifier coupled to the output of said means for subtracting; means for clipping the signal developed by said full-wave rectifier and coupled thereto, said means for clipping having a predetermined trigger level to derive an output in response to a glitch; and means coupled to said means for clipping for operating said switch in response to the output of said means for clipping, thereby to cause said track and store amplifier to revert into the store mode to thereby substantially eliminate the effects of a glitch.
Claim 2
Dependent Claim
251 words
A circuit for substantially removing the undesirable effects of a glitch caused by an error in at least one bit of a digital signal applied to a digital-to-analog converter, the analog signal in turn being utilized for controlling a machine, said circuit comprising: a source of digital signals which may include an error in at least one bit; an analog-to-digital converter coupled to said source for impressing on said converter digital signals, said converter generating output pulses, each having a duration of one sample period; a track and store amplifier coupled to said converter, said track and store amplifier including a switch, which when actuated will convert the track mode of said amplifier into the store mode; means coupled to said converter for delaying the converter output signal by one sample period; means for subtracting the output of said converter from the output of said means for delaying the converter output signal and coupled to said converter and to said means for delaying; a full-wave rectifier coupled to the output of said means for subtracting; means for clipping the signal developed by said full-wave rectifier and coupled thereto, said means for clipping having a predetermined trigger level to derive an output in response to a glitch; and means coupled to said means for clipping for operating said switch in response to the output of said means for clipping, thereby to cause said track and store amplifier to revert into the store mode to thereby substantially eliminate the effects of a glitch.
Claim 3
Dependent Claim
40 words
A circuit as defined in claim 1 wherein means for delaying the rise time of the signal from said converter is provided, said means for delaying the rise time being coupled between said converter and said track and store amplifier.
Claim 4
Dependent Claim
49 words
A circuit as defined in claim 1 wherein said means for delaying the converter output signal includes two additional track and hold amplifiers, each having a switch, and a monostable circuit having complementary outputs for operating respective ones of the switches of said two additional track and hold amplifiers.
Claim 5
Dependent Claim
22 words
A circuit as defined in claim 1 wherein said switch of said track and hold amplifier consists of a field effect transistor.
Claim 6
Dependent Claim
26 words
A circuit as defined in claim 3 wherein the two switches of said two additional track and hold amplifiers consist each of a field effect transistor.
Claim 7
Dependent Claim
42 words
A circuit as defined in claim 1 wherein said means for subtracting the converter output signal and said delayed converter output signal includes an inverter amplifier and an adder for adding the inverted converter output signal to the delayed converter output signal.
Claim 8
Dependent Claim
34 words
A circuit as defined in claim 1 wherein said means for clipping is followed by an inverter for energizing a monostable circuit, which in turn, operates the switch of said track and hold amplifier.
Claim 9
Dependent Claim
19 words
A circuit as defined in claim 3 wherein a free running oscillator is provided for controlling said monostable circuit.
Claim 10
Dependent Claim
24 words
A circuit as defined in claim 3 wherein said converter generates sample pulses, and means for impressing said sample pulses on said monostable circuit.
Claim 11
Independent Claim
137 words
The method for substantially removing the undesirable effects of a glitch caused by an error in at least one bit of a digital signal, said method comprising the steps of: converting the digital signal to an analog signal consisting of output pulses, each having a duration of one sample period; passing the output pulses to a utilization point in the absence of a glitch; delaying the output pulses by one sample period; subtracting the delayed output pulses from the output pulses; full-wave rectifying the subtracted pulses; clipping the full-wave rectified pulses to derive an output pulse above a predetermined trigger level in response to a glitch; and holding the output pulses for the duration of one sample period in response to an output pulse obtained from the clipping, thereby to substantially eliminate the effects of a glitch.
Claim 12
Independent Claim
137 words
The method for substantially removing the undesirable effects of a glitch caused by an error in at least one bit of a digital signal, said method comprising the steps of: converting the digital signal to an analog signal consisting of output pulses, each having a duration of one sample period; passing the output pulses to a utilization point in the absence of a glitch; delaying the output pulses by one sample period; subtracting the delayed output pulses from the output pulses; full-wave rectifying the subtracted pulses; clipping the full-wave rectified pulses to derive an output pulse above a predetermined trigger level in response to a glitch; and holding the output pulses for the duration of one sample period in response to an output pulse obtained from the clipping, thereby to substantially eliminate the effects of a glitch.
Claim 13
Dependent Claim
25 words
The method defined in claim 10 wherein the rise time of the converted output pulses is delayed by a small portion of a sample period.
Claim 14
Dependent Claim
28 words
The method defined in claim 10 wherein one of the converted output signal and the delayed converted output signal is inverted and subsequently added to the other signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-04-15 | 1983-10-15 | 1984-04-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-04-15 | 1987-10-15 | 1988-04-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-04-15 | 1991-10-15 | 1992-04-15 | $7700.00 | Window Closed / Lapsed |