Patent US4231023A successfully refreshed from Google Patents.
US4231023A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Binary to ternary converter
Assignee: Singer Co
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Filing: 1979-03-12
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Granted: 1980-10-28
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Expires: 1999-03-12
Abstract
Abstract A circuit for converting serial binary coded ternary information received on one line into ternary signals for transmission on two lines. The presence or absence of a pulse in a first interval is compared with the presence or absence of a pulse in the succeeding interval and a voltage representing one ternary condition is transmitted on one line if pulses are present, on another line, if pulses are absent, and no signal is transmitted if alternating pulses are received.
Inventors
- 👤 Richard C. Warner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 13:09
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4917; H04L25/4923; H03; H03M; H03M7/00; H03M7/02; H03M7/06
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
340 words
A circuit for translating ternary data being transmitted in serial binary code on one input line into ternary data coded for binary transmission on two output lines, the input data signalling a first ternary state by means of a signal alternating at an established rate for at least one cycle, a second ternary state by the presence of a signal at a first level for the period of at least one cycle, and a third ternary state by the presence of a signal at a second level for the period of at least one cycle, including (a) first means for storing the present state of the input signal during each half cycle and providing said state as an output; (b) first logic means having as inputs the output of said means for storing and said input signal and providing an output when both are at said first level; (c) second logic means having as inputs the output of said means for storing and said input signal and providing an output when both are at said second level; (d) second means for storing the state of the output of said first logic means and providing said state as an output; (e) third means for storing the state of the output of said second logic means and providing said state as an output; and (f) a clock developing a clock signal occurring each half cycle synchronously with said input signal, each of said first, second and third means for storing responsive to said clock signal to store the state at their respective inputs and provide said states at their outputs, whereby, when said input signal remains at said first level for two half cycles, an output will be provided from said second means, when said input signal is at said second level for two half cycles, said third means for storing will provide an output and when said signal alternates between said first and second levels over a cycle, neither of said second and third means for storing will provide an output.
Claim 2
Dependent Claim
340 words
A circuit for translating ternary data being transmitted in serial binary code on one input line into ternary data coded for binary transmission on two output lines, the input data signalling a first ternary state by means of a signal alternating at an established rate for at least one cycle, a second ternary state by the presence of a signal at a first level for the period of at least one cycle, and a third ternary state by the presence of a signal at a second level for the period of at least one cycle, including (a) first means for storing the present state of the input signal during each half cycle and providing said state as an output; (b) first logic means having as inputs the output of said means for storing and said input signal and providing an output when both are at said first level; (c) second logic means having as inputs the output of said means for storing and said input signal and providing an output when both are at said second level; (d) second means for storing the state of the output of said first logic means and providing said state as an output; (e) third means for storing the state of the output of said second logic means and providing said state as an output; and (f) a clock developing a clock signal occurring each half cycle synchronously with said input signal, each of said first, second and third means for storing responsive to said clock signal to store the state at their respective inputs and provide said states at their outputs, whereby, when said input signal remains at said first level for two half cycles, an output will be provided from said second means, when said input signal is at said second level for two half cycles, said third means for storing will provide an output and when said signal alternates between said first and second levels over a cycle, neither of said second and third means for storing will provide an output.
Claim 3
Dependent Claim
16 words
The circuit of claim 1 wherein each of said means for storing comprise a D-type flip-flop.
Claim 4
Dependent Claim
22 words
The circuit of claim 2 wherein said first logic means comprise an AND gate and said second logic means a NOR gate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-10-28 | 1984-04-28 | 1984-10-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-10-28 | 1988-04-28 | 1988-10-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-10-28 | 1992-04-28 | 1992-10-28 | $7700.00 | Window Closed / Lapsed |