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US4237600A
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Method for fabricating stacked semiconductor diodes for high power/low loss applications
Assignee: RCA Corp
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Filing: 1978-11-16
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Granted: 1980-12-09
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Expires: 1998-11-16
Abstract
Abstract A semiconductor wafer is appropriately doped to create a P-N or P-I-N junction, and metallized on both its planar surfaces with electrode material. The wafer is then bonded to a second similarly processed wafer. Without damaging the semiconductor material, the stacked wafer is processed so as to delineate a plurality of diodes on each side of the center metallization, such that the diodes on each side are registered with each other. The center metallization is then cut so as to yield a plurality of stacked semiconductor diodes.
Inventors
- 👤 Arye Rosen
- 👤 Anna M. Gombar
- 👤 Edward Mykietyn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:10
CPC Classifications
H; H10; H10D; H10D8/00; H10D8/01; H10W; H10W20/00; H10W20/40; H10W90/00; Y; Y10; Y10S; Y10S148/00; Y10S148/028
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
138 words
A method for batch fabricating stacked semiconductor devices, wherein the stack consists of two diodes, comprising the steps of: (a) depositing a metallization layer on both planar surfaces of two appropriately doped semiconductor wafers; (b) bonding one wafer to the second wafer such that they form a stacked, concentric configuration with complete surface contact; (c) generating a plurality of electrode areas on both planar surfaces of the stacked wafer, such that the electrode areas on each surface are registered with each other; (d) etching through the semiconductor material on both sides of the stacked wafer, using the electrode areas as an etch mask, such that the metallization layer at the center of the stack is exposed; and, (e) separating the stacked wafer along the exposed center metallization boundaries, so as to create a plurality of stacked semiconductor devices.
Claim 2
Independent Claim
138 words
A method for batch fabricating stacked semiconductor devices, wherein the stack consists of two diodes, comprising the steps of: (a) depositing a metallization layer on both planar surfaces of two appropriately doped semiconductor wafers; (b) bonding one wafer to the second wafer such that they form a stacked, concentric configuration with complete surface contact; (c) generating a plurality of electrode areas on both planar surfaces of the stacked wafer, such that the electrode areas on each surface are registered with each other; (d) etching through the semiconductor material on both sides of the stacked wafer, using the electrode areas as an etch mask, such that the metallization layer at the center of the stack is exposed; and, (e) separating the stacked wafer along the exposed center metallization boundaries, so as to create a plurality of stacked semiconductor devices.
Claim 3
Dependent Claim
22 words
A method in accordance with claim 1, wherein the bonding is accomplished by soldering across the entire interface between the two wafers.
Claim 4
Dependent Claim
53 words
A method in accordance with claim 1, wherein prior to metallization, each of the semiconductor wafers is doped so as to create a surface layer of N-type conductivity, an opposite surface layer of P-type conductivity, and a P-N junction in the interior of the wafer, at the interface of the two surface layers.
Claim 5
Dependent Claim
46 words
A method in accordance with claim 1, wherein prior to metallization, each of the semiconductor wafers is doped so as to create a P-I-N junction, with a surface layer of N-type conductivity, an opposite surface layer of P-type conductivity, and an intermediate layer of intrinsic semiconductor.
Claim 6
Dependent Claim
23 words
A method in accordance with claim 1, wherein the metallization layer is comprised of a gold thin film overlying a chromium thin film.
Claim 7
Dependent Claim
32 words
A method in accordance with claim 5 wherein after bonding the two wafers, additional gold metallization is deposited on the gold thin film layer which covers each surface of the stacked wafer.
Claim 8
Independent Claim
46 words
A method in accordance with claims 1 or 6, wherein the electrode areas are delineated by generating a photoresist pattern on the metallization on each surface of the stacked wafer; removing the metallization from the areas which are not covered by photoresist; and, removing the photoresist.
Claim 9
Dependent Claim
28 words
A method in accordance with claim 7, wherein the steps of generating the photoresist pattern, removing the metallization, and removing the photoresist, are performed on both surfaces simultaneously.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-12-09 | 1984-06-09 | 1984-12-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-12-09 | 1988-06-09 | 1988-12-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-12-09 | 1992-06-09 | 1992-12-09 | $7700.00 | Window Closed / Lapsed |