Patent US4249119A successfully refreshed from Google Patents.
US4249119A
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Digital drive circuit for electric motor or the like
Assignee: RCA Corp
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Filing: 1978-12-18
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Granted: 1981-02-03
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Expires: 1998-12-18
Abstract
Abstract A digital drive current for application to a variable-speed electric motor is generated from a binary signal including N high-order bits and n low-order bits. A pulse waveform of fixed frequency higher than the frequency to which the motor can respond is generated to have a pulse width duty cycle in accordance with the value of the high-order bits. The low-order bits are used to make a one-step increase in the width of a proportion, determined by the value of the low-order bits, of the pulses of the pulse waveform, so that the average pulse width is increased a desired fraction of one step.
Inventors
- 👤 Anthony D. Robbi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 22:03
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/18; G05B19/416; G06; G06F; G06F1/00; G06F1/02; G06F1/025; H; H02; H02P; H02P23/00; H02P23/22; F; F02; F02B; F02B75/00; F02B75/02; F02B2075/022; F02B2075/027; G05B2219/00; G05B2219/30; G05B2219/42; G05B2219/42237; Y; Y10; Y10S; Y10S388/00; Y10S388/907; Y10S388/912; Y10S388/922
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
122 words
Means to generate a variable electric drive signal for application to a utilization device, comprising a source of a binary signal representing a desired drive current amplitude, said signal including N high-order bits and n low-order bits, first means to generate a pulse waveform having a fixed frequency f o higher than the frequency to which the utilization device can respond, having a variable pulse width duty cycle, and having pulses with widths in accordance with the value of said high-order bits, whereby the pulses may have any one of 2 N discrete widths, and second means to make an increase in the widths of a proportion of the pulses of said pulse waveform determined by the value of said low-order bits.
Claim 2
Dependent Claim
122 words
Means to generate a variable electric drive signal for application to a utilization device, comprising a source of a binary signal representing a desired drive current amplitude, said signal including N high-order bits and n low-order bits, first means to generate a pulse waveform having a fixed frequency f o higher than the frequency to which the utilization device can respond, having a variable pulse width duty cycle, and having pulses with widths in accordance with the value of said high-order bits, whereby the pulses may have any one of 2 N discrete widths, and second means to make an increase in the widths of a proportion of the pulses of said pulse waveform determined by the value of said low-order bits.
Claim 3
Dependent Claim
13 words
The combination of claim 1 wherein said utilization device is an electric motor.
Claim 4
Dependent Claim
26 words
The combination of claim 1 wherein said second means makes a one-step increase equal to 2 -N in the widths of a proportion of the pulses.
Claim 5
Dependent Claim
63 words
The combination of claim 1 wherein said first means includes a source of a first clock signal, an N-bit counter driven by the first clock signal, and an N-bit comparator receptive to the count in said N-bit counter and the N high-order bits from said source of a binary signal and having an output providing said pulse waveform of frequency f o .
Claim 6
Dependent Claim
38 words
The combination of claim 4 wherein said N-bit comparator provides a "high" output solely when the count in the N-bit counter is less than the value of the N high-order bits from said source of a binary signal.
Claim 7
Dependent Claim
84 words
The combination of claim 5 wherein said second means includes an n-bit counter driven by a clock signal having a frequency which is a submultiple of the frequency of said first clock, and an n-bit comparator receptive to the count in said n-bit counter and the n low-order bits from said source of a binary signal and having an output providing a pulse wave having a fixed frequency f m and having pulses with widths in accordance with the value of said high-order bits.
Claim 8
Dependent Claim
38 words
The combination of claim 6 wherein said n-bit comparator provides a "high" output solely when the count in the n-bit counter is less than the value of the n low-order bits from said source of a binary signal.
Claim 9
Dependent Claim
55 words
The combination of claim 7 wherein said second means also includes a logic circuit operative whenever a pulse in the waveform of frequency f o occurs during a pulse in the waveform of frequency f m to cause a one-step increase in the width of a pulse in the waveform of frequency f o .
Claim 10
Dependent Claim
21 words
The combination of claim 8 wherein said logic circuit includes a time delay unit, and "and" gate and an "or" gate.
Claim 11
Dependent Claim
12 words
The combination of claim 8 wherein said logic circuit includes an incrementer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-02-03 | 1984-08-04 | 1985-02-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-02-03 | 1988-08-04 | 1989-02-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-02-03 | 1992-08-04 | 1993-02-03 | $7700.00 | Window Closed / Lapsed |