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US4271331A Expired / Lapsed US ⏱️ 0.0 years remaining

Analog processing system for real-time conversion of the frequency of analog signals

Assignee: IN MAR ELECTRONICS
•
Filing: 1979-06-27
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Granted: 1981-06-02
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Expires: 1999-06-27
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Abstract

Abstract An analog signal processing system is described for changing the frequency of analog signals in a real-time manner. The system includes at least two analog shift registers, (specifically, three analog shift registers), an input circuit connecting the input end of all the registers in parallel, an output circuit selectively connectable to the output ends of the registers, a high frequency clock pulse source, a lower frequency clock pulse source, and cyclically operable switching means effective to load from the input circuit at least one analog shift register at the rate corresponding to the frequency of one of the clock pulses, while unloading at least one other register into the output circuit at the rate corresponding to the frequency of the other clock pulses. Two applications are described, for purposes of example. One application is as a hearing aid device to reduce the frequency of audio signals in a real-time manner for a person having a limited-frequency audibility. The other application is a communication device for the real-time transmission and reception of audio signals rendering them unintelligible except by receivers equipped with a processing system for reducing the frequency of the received signals.

Inventors

  • 👤 Arie Kalkstein

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 17:22
CPC Classifications
H; H04; H04R; H04R25/00; H04R25/35; H04R25/353; H04B; H04B1/00; H04B1/66; H04B1/662; H04K; H04K1/00; H04K1/04

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 186 words
An analog signal processing system, comprising: (a) three analog shift registers each capable of storing, under the control of loading clock pulses, an analog signal in the form of a plurality of analog samples, and of outputting them under the control of unloading clock pulses; (b) a source of high-frequency clock pulses; (c) a source of lower-frequency clock pulses; (d) an input circuit connected to the input end of all the analog shift registers in parallel; (e) an output circuit selectively connectable to the output ends of the analog shift registers; and (f) cyclically operable switching means effective: (i) during a first phase, to unload one register at the high-frequency clock pulse rate while loading a second and a third register at the low-frequency clock pulse rate. (ii) during a second phase, to unload said second register at the high-frequency clock pulse rate, while loading said first and third registers at the low-frequency clock pulse rate; and (iii) during a third phase, to unload said third register at the high-frequency clock pulse rate, while loading said first and second registers at the low-frequency clock pulse rate.
Claim 2
Dependent Claim 186 words
An analog signal processing system, comprising: (a) three analog shift registers each capable of storing, under the control of loading clock pulses, an analog signal in the form of a plurality of analog samples, and of outputting them under the control of unloading clock pulses; (b) a source of high-frequency clock pulses; (c) a source of lower-frequency clock pulses; (d) an input circuit connected to the input end of all the analog shift registers in parallel; (e) an output circuit selectively connectable to the output ends of the analog shift registers; and (f) cyclically operable switching means effective: (i) during a first phase, to unload one register at the high-frequency clock pulse rate while loading a second and a third register at the low-frequency clock pulse rate. (ii) during a second phase, to unload said second register at the high-frequency clock pulse rate, while loading said first and third registers at the low-frequency clock pulse rate; and (iii) during a third phase, to unload said third register at the high-frequency clock pulse rate, while loading said first and second registers at the low-frequency clock pulse rate.
Claim 3
Dependent Claim 36 words
A system according to claim 1, wherein said output circuit includes a low-pass filter which substantially reconstructs the original analog signal but at a different frequency determined by the frequency relationship of the two clock pulses.
Claim 4
Dependent Claim 46 words
The system according to claim 1, wherein said input circuit includes a microphone for converting audio signals to electrical analog signals, and wherein said output circuit further includes a converter for converting the outputted analog signals to sound having a higher-frequency than the original audio signals.
Claim 5
Dependent Claim 22 words
A system according to claim 1, wherein the frequency of the lower-frequency clock pulses is one-half that of the high-frequency clock pulses.
Claim 6
Dependent Claim 39 words
Apparatus comprising a plurality of stages of analog signal processing systems, each stage being according to claim 1, all said stages being connected in tandem, the frequency of the lower-frequency clock pulses being one-half that of the high-frequency pulses.

References Cited (Backward Citations)

US3950617A Cited
US3949174A Cited
US4003027A Cited
US4186643A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1984-06-01 1984-12-01 1985-06-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1988-06-01 1988-12-01 1989-06-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1992-06-01 1992-12-01 1993-06-02 $7700.00 Window Closed / Lapsed

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