Coincidence analysis circuit for positron annihilation imaging device

Claim 1

A coincidence detector circuit for receiving a plurality of pulsed input signals, pairs of which occur within a selected coincidence resolving time and require to be identified, said detector circuit comprising: (a) input means for receiving pulsed input signals and converting them into level discriminated signals; (b) a multiple bit delay to which the level discriminated signals are applied for generating output signals corresponding to and delayed with respect to the level discriminated signals; (c) a multiple bit holding register connected to receive the delayed output signals from said multiple bit delay for generating holding register output signals which are the multiple bit delay outputs at the selected coincidence resolving time after the occurrence of any of the pulsed input signals; (d) a plurality of priority encoders connected to receive output signals from said holding register, said encoders having a plurality of groups of output signals, each of which contains an address of the most significant input, and a further output signal when one or more input signals are present, and including a parity verification circuit for analyzing the further output signal and applying the groups of output signals and the further output signal as an overall output signal from the plurality of priority encoders when the parity is even; (e) a multiple bit validation register receiving the overall output signal from said plurality of priority encoders, said validation register retaining even parity pairs of said pulsed input signals in an encoded form for a predetermined time; (f) a high group priority encoder connected to receive output signals from said validation register, for generating an address during the predetermined time, following which the even parity pairs of output signals are received, said priority encoder having outputs which together contain the address of the most significant priority encoder receiving outputs from the holding register; (g) a high group decoder connected to receive output signals from said high group priority encoder, said high group decoder regenerating the highest numbered input to said high group priority encoder; (h) a high group mask connected to receive the regenerated inputs from said high group decoder, said high group mask eliminating the highest numbered input; (i) a low group priority encoder connected to receive output signals from said high group mask and having outputs which together contain the address of a second priority encoder receiving outputs from the holding register, after an appropriate propagation delay; (j) a low group decoder connected to receive the address from said low group priority encoder; (k) a low group mask connected to receive output signals from said low group decoder and from said high group mask, for generating output signals; (l) a further priority encoder, eliminating events in which an even number of detectors other than two respond, connected to receive the output signals from said low group mask; and (m) a plurality of high and low group multiplexers receiving said plurality of groups of output signals from said validation register, said high group multiplexers having output address signals corresponding to the most significant input signals of said plurality of input signals, said low group multiplexers having output address signals corresponding to the least significant group of input signals of said plurality of input signals the outputs from said high group and low group priority encoders and high group and low group multiplexers generating a unique address for both detectors after an appropriate propagation delay.