Patent US2949599A successfully refreshed from Google Patents.
Patent US4348253A successfully refreshed from Google Patents.
US4348253A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for fabricating via holes in a semiconductor wafer
Assignee: RCA Corp
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Filing: 1981-11-12
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Granted: 1982-09-07
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Expires: 2001-11-12
Abstract
Abstract A circuit pattern is formed on a front side surface of a semiconductor wafer and an apertured photoresist pattern is formed over the circuit pattern. Via holes are then formed by laser irradiating the wafer at sites corresponding to the photoresist apertures. The back side surface of the wafer is next metallized and this surface is adhered to a plating block by means of an adhesive layer. Electrical connection between the substrate and plating block is then made, the via holes are electroplated, and the substrate is separated from the plating block and adhesive layer.
Inventors
- 👤 Saligrama N. Subbarao
- 👤 Ho-Chung Huang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:01
CPC Classifications
H; H10; H10P; H10P34/00; H10P34/40; H10P34/42; H10W; H10W20/00; H10W20/01; H10W20/021; H10W20/023; H10W20/0238; H10W20/20; H10W72/00; H10W72/30; Y; Y10; Y10S; Y10S156/00; Y10S156/934; Y10S156/941; Y10T; Y10T156/00; Y10T156/19
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
88 words
A method for fabricating a conductive via hole in a semiconductor wafer, comprising: forming a layer of apertured photoresist on a first wafer surface; laser drilling a via hole through said wafer, at a site corresponding to said photoresist aperture; metallizing a second wafer surface opposing the first surface; placing the second wafer surface on an adhesive layer on a plating block; electrically connecting the second surface metallization to the plating block; electroplating through the via hole; and separating the wafer from the plating block and adhesive layer.
Claim 2
Independent Claim
88 words
A method for fabricating a conductive via hole in a semiconductor wafer, comprising: forming a layer of apertured photoresist on a first wafer surface; laser drilling a via hole through said wafer, at a site corresponding to said photoresist aperture; metallizing a second wafer surface opposing the first surface; placing the second wafer surface on an adhesive layer on a plating block; electrically connecting the second surface metallization to the plating block; electroplating through the via hole; and separating the wafer from the plating block and adhesive layer.
Claim 3
Dependent Claim
18 words
A method in accordance with claim 1, wherein the wafer includes a circuit pattern on said first surface.
Claim 4
Dependent Claim
24 words
A method in accordance with claim 2, further comprising forming said apertured photoresist layer such that the aperture is located over the circuit pattern.
Claim 5
Dependent Claim
16 words
A method in accordance with claim 1, comprising drilling said via hole with a YAG laser.
Claim 6
Dependent Claim
13 words
A method in accordance with claim 1, wherein said adhesive layer comprises photoresist.
Claim 7
Dependent Claim
30 words
A method in accordance with claim 1, comprising painting an electrically conductive material on the periphery of the wafer so as to electrically connect the wafer to the plating block.
Claim 8
Dependent Claim
26 words
A method in accordance with claim 6, wherein the wafer is separated from the plating block by dissolving the adhesive layer and the electrically conductive paint.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-09-06 | 1986-03-08 | 1986-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-09-06 | 1990-03-08 | 1990-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-09-06 | 1994-03-08 | 1994-09-07 | $7700.00 | Window Closed / Lapsed |