US4360898A
Expired / Lapsed
US
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Programmable logic array system incorporating Josephson devices
Assignee: International Business Machines Corp
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Filing: 1980-06-30
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Granted: 1982-11-23
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Expires: 2000-06-30
Abstract
Abstract A Programmable Logic Array (PLA) system which utilizes Josephson devices and the noninverting capabilities of these devices is disclosed. The disclosed PLA system includes a personalized Read Only Memory (ROM) which is adapted to store the applied input signals as well as the output signals which are a logic function of the input signals. As soon as outputs from the ROM are available, an interface circuit which may be timed or untimed, inverting or noninverting provides output signals which can be utilized to drive other logic circuits or to act as inputs to another personalized Read Only Memory (ROM). The latter provides another logic function of the inputs at its outputs. Again, the outputs may be used directly or applied to another interface circuit which itself may provide inverted or noninverted outputs. Like the first mentioned ROM, the second mentioned ROM is capable of storing its inputs and the resulting outputs which are some logic function of the inputs as a result of the ROM personalization. The ROM's involved utilize memory cells which are programmable Josephson junction devices operating in a liquid helium environment. The programmable logic array system is disclosed in a full adder embodiment which is dc powered. A similar hybrid embodiment using both ac and dc power is also shown. The resulting system using high density ROM's provides high speed logic using relatively standard loop circuits which minimize the effect of the presence of resonances of known random logic circuits.
Inventors
- 👤 Sadeg M. Faris
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 06:23
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/195; H03K19/1952; Y; Y10; Y10S; Y10S505/00; Y10S505/825; Y10S505/831; Y10S505/832
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
57 words
A programmable logic array system comprising: means for generating a plurality of input signals, and, superconducting read-only memory means connected to said generating means for converting said input signals to output signals different from said input signals for simultaneously storing said input and output signals in said read-only memory means in the absence of further input signals.
Claim 2
Dependent Claim
57 words
A programmable logic array system comprising: means for generating a plurality of input signals, and, superconducting read-only memory means connected to said generating means for converting said input signals to output signals different from said input signals for simultaneously storing said input and output signals in said read-only memory means in the absence of further input signals.
Claim 3
Dependent Claim
26 words
A programmable logic array system according to claim 1 further including means responsive to said output signals connected to said means for simultaneously converting and storing.
Claim 4
Dependent Claim
21 words
A programmable logic array system according to claim 1 wherein said means for generating includes a plurality of pulsed current sources.
Claim 5
Dependent Claim
52 words
A programmable logic array system according to claim 1 wherein said means for converting said input signals and simultaneously storing said input and output signals includes a memory array which includes a plurality of personalized Josephson junction memory cells the output of which is a stored logic function of said input signals.
Claim 6
Dependent Claim
29 words
A programmable logic array system according to claim 1 wherein said means for converting and simultaneously storing said input and output signals includes a plurality of superconducting storage loops.
Claim 7
Dependent Claim
21 words
A programmable logic array system according to claim 2 wherein said means for generating includes a plurality of pulsed current sources.
Claim 8
Dependent Claim
52 words
A programmable logic array system according to claim 2 wherein said means for converting said input signals and simultaneously storing said input and output signals includes a memory array which includes a plurality of personalized Josephson junction memory cells the output of which is a stored logic function of said input signals.
Claim 9
Dependent Claim
42 words
A programmable logic array system according to claim 2 wherein said means responsive to said output signals includes means for providing noninverted output signals connected to said means for converting said input signals and for simultaneously storing said input and output signals.
Claim 10
Dependent Claim
42 words
A programmable logic array system according to claim 2 wherein said means responsive to said output signals includes means for providing inverted output signals connected to said means for converting said input signals and for simultaneously storing said input and output signals.
Claim 11
Dependent Claim
28 words
A programmable logic array system according to claim 4 wherein said plurality of pulsed current sources generate pulses which are the true and complement of said input signals.
Claim 12
Dependent Claim
21 words
A programmable logic array system according to claim 4 wherein said means for generating includes a plurality of pulsed current sources.
Claim 13
Dependent Claim
26 words
A programmable logic array system according to claim 5 further including means responsive to said output signals connected to said means for converting and simultaneously storing.
Claim 14
Dependent Claim
42 words
A programmable logic array system according to claim 7 wherein said means responsive to said output signals includes means for providing noninverted output signals connected to said means for converting said input signals and for simultaneously storing said input and output signals.
Claim 15
Dependent Claim
41 words
A programmable logic system according to claim 7 wherein said means responsive to said output signals includes means for providing inverted output signals connected to said means for converting said input signals and for simultaneously storing said input and output signals.
Claim 16
Dependent Claim
49 words
A programmable logic array system according to claim 8 wherein said means responsive to said output signals further includes means connected to said means for providing for converting said noninverted output signals to other output signals and for simultaneously storing said noninverted output signals and said other output signals.
Claim 17
Dependent Claim
49 words
A programmable logic array system according to claim 9 wherein said means responsive to said output signal further includes means connected to said means for providing for converting said inverted output signals to other output signals and for simultaneously storing said inverted output signals and said other output signals.
Claim 18
Dependent Claim
53 words
A programmable logic array system according to claim 10 wherein said means for converting said input signals and simultaneously storing said input and said output signals includes a memory array which includes a plurality of personalized Josephson junction memory cells the output of which is a stored logic function of said input signals.
Claim 19
Dependent Claim
26 words
A programmable logic array system according to claim 15 further including means responsive to said output signals connected to said means for converting and simultaneously storing.
Claim 20
Dependent Claim
91 words
A programmable logic array system according to claim 12 wherein said means responsive to said output signals includes means for providing noninverted output signals connected to said means for converting said input signals and for simultaneously storing said input and output signals, means connected to said means for providing for converting said noninverted output signals to other output signals and for simultaneously storing said noninverted output signals and said other output signals, and, means responsive to said other output signals connected to said last mentioned means for converting and simultaneously storing.
Claim 21
Dependent Claim
90 words
A programmable logic array system according to claim 12 wherein said means responsive to said output signals includes means for providing inverted output signals connected to said means for converting said input signals and simultaneously storing said input and output signals, means connected to said means for providing for converting said inverted output signals to other output signals and for simultaneously storing said inverted output signals and said other output signals, and, means responsive to said other output signals connected to said last mentioned means for converting and simultaneously storing.
Claim 22
Dependent Claim
68 words
A programmable logic array system according to claim 13 wherein said means responsive to said output signals further includes means connected to said means for providing for converting said noninverted output signals to other output signals and for simultaneously storing said noninverted output signals and said other output signals, and, means responsive to said other output signals connected to said last mentioned means for converting said simultaneously storing.
Claim 23
Dependent Claim
69 words
A programmable logic array system according to claim 14 wherein said means responsive to said output signals further includes means for connected to said means for providing for converting said inverted output signals to other input signals and for simultaneously storing said inverted output signals and said other output signals, and, means responsive to said other output signals connected to said last mentioned means for converting and simultaneously storing.
Claim 24
Dependent Claim
50 words
A programmable logic array system according to claim 20 wherein said means for converting said noninverted output signals to other output signals includes a memory array which includes a plurality of personalized Josephson junction memory cells the output of which is a stored logic function of said noninverted output signals.
Claim 25
Dependent Claim
50 words
A programmable logic array system according to claim 16 wherein said means for converting said inverted output signals to other output signals includes a memory array which includes a plurality of personalized Josephson junction memory cells the output of which is a stored logic function of said inverted output signals.
Claim 26
Dependent Claim
56 words
A programmable logic array system according to claim 17 wherein said Josephson junction memory cells are arranged in a plurality of storage loops each of said loops including a smaller plurality of said memory cells arranged in series, and, means connected to each of said loops for applying gate current to each of said memory cells.
Claim 27
Dependent Claim
38 words
A programmable logic array system according to claim 18 wherein said means responsive to said output signals includes means for providing output signals connected to said means for converting said input signals and simultaneously storing said output signals.
Claim 28
Dependent Claim
69 words
A programmable logic array system according to claim 19 wherein said means for providing includes a plurality of Josephson junction circuits each of which switches in response to the presence of an output signal delivering a replica of said output signals to said means for converting said output signals to other signals and, wherein said means responsive to said other output signals includes means for inverting said other signals.
Claim 29
Dependent Claim
48 words
A programmable logic array system according to claim 21 wherein said means for converting and storing said other output signals includes a memory array which includes a plurality of personalized Josephson junction memory cells the output of which is a stored logic function of said noninverted output signals.
Claim 30
Dependent Claim
48 words
A programmable logic array system according to claim 22 wherein said means for converting and storing said other output signals includes a memory array which includes a plurality of personalized Josephson junction memory cells the output of which is a stored logic function of said inverted output signals.
Claim 31
Dependent Claim
67 words
A programmable logic array system according to claim 25 wherein said means for applying gate current includes a source of direct current, a Josephson junction shunting each of said loops, each of said junctions being disposed in series with said source of direct current, and means for simultaneously switching each of said junction to place each of said loops in series with said source of direct current.
Claim 32
Dependent Claim
67 words
A programmable logic array system according to claim 25 wherein said means for applying gate current includes a source of alternating current, a Josephson junction shunting each of said loops, each of said junctions being disposed in series with said source of alternating current, and means for simultaneously switching each of said junctions to place each of said loops in series with said source of alternating current.
Claim 33
Dependent Claim
59 words
A programmable logic array system according to claim 30 further including a plurality of control lines each one connected to a respective one of said pulsed current sources and disposed in electromagnetically coupled relationship with a plurality of said Josephson junction memory cells each one of said plurality of Josephson junction memory cells being disposed in a different loop.
Claim 34
Dependent Claim
59 words
A programmable logic array system according to claim 31 further including a plurality of control line each one connected to a respective one of said pulsed current sources and disposed in electromagnetically coupled relationship with a plurality of said Josephson junction memory cells each one of said plurality of Josephson junction memory cells being disposed in a different loop.
References Cited (Backward Citations)
US3849276A
Cited
US3758795A
Cited
US3913120A
Cited
US4130893A
Cited
US4198577A
Cited
US4151605A
Cited
US4149097A
Cited
US4210921A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-11-22 | 1986-05-24 | 1986-11-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-11-22 | 1990-05-24 | 1990-11-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-11-22 | 1994-05-24 | 1994-11-23 | $7700.00 | Window Closed / Lapsed |