Power failure early warning circuit for microprocessor with CMOS RAM memory

Claim 1

In a microprocessor based product having a CMOS random access memory connected to the microprocessor for storing data and a dc power supply for said microprocessor and memory derived from a primary ac source, apparatus for preserving the data in memory and for preventing incorrect transfers by said microprocessor when there is a loss of primary ac power, comprising: means operable in direct response to the loss of primary ac power and independent of the dc supply to produce a first signal; means operable in response to said first signal to prevent initiation of the transfer of data from said microprocessor to said memory; and means directly responsive to the loss of primary ac power and independent of the dc supply for producing a second signal on the CMOS RAM ENABLE line of the memory a predetermined time after said first signal so as to disable said memory and place it in standby condition, said predetermined time being a period which is shorter than the period required for the voltage of the dc supply to decay below that level necessary to provide for correct transfer to memory but longer than the period for transfer of a complete block of data.