Patent US4380034A successfully refreshed from Google Patents.
US4380034A
Expired / Lapsed
US
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Track centering servo pulse noise filter
Assignee: Seagate Technology LLC
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Filing: 1980-09-26
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Granted: 1983-04-12
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Expires: 2000-09-26
Abstract
Abstract A track centering servo pulse noise filter is provided. Prerecorded pulses on a disk track's even and odd half tracks are sensed by the disk's read head, preamplified, DC biased, peak detected, and stored on a FIFO basis into a noise filter comprising two sets of N analog sample and hold cells, one set for the even pulses and one set for the odd pulses. The output of each even-pulse sample and hold cell is input to a summing junction to form an average of the last N pulses. The same is done with the outputs of the odd-pulse sample and hold cells. The two summing junctions are then input to a differential amplifier to form a position error signal to the disk head track centering servo system for keeping the head centered on the track.
Inventors
- 👤 Guss L. Krake
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 12:22
CPC Classifications
G; G11; G11B; G11B21/00; G11B21/02; G11B21/10; G11B21/106
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
180 words
In a disk track centering servo system having even pulses written on one servo track and odd pulses written on an adjacent servo track, a read head for reading information, including said pulses, means for preamplifying said pulses, and means for distinguishing between odd and even pulses, the improvment comprising: first and second pluralities of analog sample and hold circuits, each having an output; means for inputting even pulses, one pulse per circuit, into said first plurality of said circuits; said first circuits holding the latest received N pulses, where N is a predetermined number; means for inputting odd pulses, one pulse per circuit, into said second plurality of said circuits; said second circuits holding the latest received N pulses, where N is a predetermined number; means for analog summing the outputs of said first plurality of circuits to form a first sum; means for analog summing the outputs of said second plurality of circuits to form a second sum; and means for deriving the difference between said first sum and said second sum to form a position error signal.
Claim 2
Dependent Claim
180 words
In a disk track centering servo system having even pulses written on one servo track and odd pulses written on an adjacent servo track, a read head for reading information, including said pulses, means for preamplifying said pulses, and means for distinguishing between odd and even pulses, the improvment comprising: first and second pluralities of analog sample and hold circuits, each having an output; means for inputting even pulses, one pulse per circuit, into said first plurality of said circuits; said first circuits holding the latest received N pulses, where N is a predetermined number; means for inputting odd pulses, one pulse per circuit, into said second plurality of said circuits; said second circuits holding the latest received N pulses, where N is a predetermined number; means for analog summing the outputs of said first plurality of circuits to form a first sum; means for analog summing the outputs of said second plurality of circuits to form a second sum; and means for deriving the difference between said first sum and said second sum to form a position error signal.
Claim 3
Dependent Claim
17 words
Apparatus according to claim 1 wherein each of said pluralities of circuits comprises an analog shift register.
Claim 4
Dependent Claim
90 words
Apparatus according to claim 2 wherein each of said analog shift registers includes a series of interconnected gate-capacitor pairs, the control means of the gate and one terminal of the capacitor of a first, third, fifth and succeeding odd numbered pairs connected to a first clock, the control means of the gate and one terminal of the capacitor of a second, fourth, sixth and succeeding even numbered pairs connected to a second clock oppositely polarized from said first clock and means supplying said first and second clocks to said registers.
Claim 5
Dependent Claim
30 words
Apparatus of claim 3 wherein said gates comprise MOS FET's and further including an additional MOS FET interconnected between each of said pairs, the gate of which is biased on.
Claim 6
Dependent Claim
48 words
Apparatus of claim 3 wherein said analog shift register further includes an input gate, the control means of which is connected to said second clock, and a capacitor connected to receive the charge transferred through said input gate and further connected to the gate of said first pair.
Claim 7
Dependent Claim
63 words
Apparatus according to claim 1 wherein ech of said inputting means includes multiplexer means for addressing a given one of said circuits according to a count on its control inputs, and counter means for counting each time a pulse is input to a circuit and placing that count on said multiplexor's control inputs; said counter means' count overflowing to zero after N-1 counts.
Claim 8
Dependent Claim
33 words
Apparatus according to claim 6 wherein each of said circuits comprises: an input line; a capacitor interconnected between said line and ground; and a voltage-follower means having its input connected to said line.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-04-11 | 1986-10-11 | 1987-04-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-04-11 | 1990-10-11 | 1991-04-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-04-11 | 1994-10-11 | 1995-04-12 | $7700.00 | Window Closed / Lapsed |