US4383304A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable bit shift circuit
Assignee: Pioneer Corp
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Filing: 1980-10-06
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Granted: 1983-05-10
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Expires: 2000-10-06
Abstract
Abstract A programmable bit shift circuit in which data can be shifted in one operation by as many bit positions as desired, m input data lines and n output data lines are provided intersecting each other with n>m. Switching elements such as transmission gates are provided at intersections of the input and output data lines. The control electrodes of switching elements at the intersections of the first through m-th input data lines and the j-th through (j+m-l)-th output data lines for each integer value of j equal to or less than (n-m+l) are interconnected. Shift control signals are coupled to the interconnected control electrodes.
Inventors
- 👤 Kunihiko Hirashima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 19:54
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/01; G06F5/015
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
210 words
A programmable bit shift circuit for shifting an input multi-bit binary number selectively either leftwardly or rightwardly in a single step, comprising: m input data lines; n output data lines, where n is at least m+2; k control lines, where k is at least 3 and is equal to a total number of possible bit position shifts in both leftward and rightward directions plus 1; and k·m switching elements arranged in a k-by-m rectangular array, each of said input data lines being connected to inputs of each of said switching elements in a corresponding row of said array, each of said control lines being connected to control electrodes of each of said switching elements in a corresponding column of said array, and each of said output lines being connected to outputs of said switching elements along a corresponding diagonal line of said array; wherein said input data is shifted by a selected predetermined number of bit positions in a desired one of leftward and rightward directions by activating a selected one of said control lines corresponding to said selected predetermined number of bit positions and said desired one of leftward and rightward directions with a delay determined entirely by a delay time of a single one of said switching elements.
Claim 2
Dependent Claim
210 words
A programmable bit shift circuit for shifting an input multi-bit binary number selectively either leftwardly or rightwardly in a single step, comprising: m input data lines; n output data lines, where n is at least m+2; k control lines, where k is at least 3 and is equal to a total number of possible bit position shifts in both leftward and rightward directions plus 1; and k·m switching elements arranged in a k-by-m rectangular array, each of said input data lines being connected to inputs of each of said switching elements in a corresponding row of said array, each of said control lines being connected to control electrodes of each of said switching elements in a corresponding column of said array, and each of said output lines being connected to outputs of said switching elements along a corresponding diagonal line of said array; wherein said input data is shifted by a selected predetermined number of bit positions in a desired one of leftward and rightward directions by activating a selected one of said control lines corresponding to said selected predetermined number of bit positions and said desired one of leftward and rightward directions with a delay determined entirely by a delay time of a single one of said switching elements.
Claim 3
Dependent Claim
18 words
The bit shift circuit of claim 1 wherein each of said switching elements comprises a C-MOS transmission gate.
Claim 4
Dependent Claim
45 words
The bit shift circuit of either of claims 2 and 1 further comprising an OR gate for combining signals representing zero left and right shifts, said OR gate having an output connected to a predetermined one of said control lines corresponding to a zero shift.
Claim 5
Dependent Claim
55 words
The bit shift circuit of claim 2 wherein each said control line comprises a normal control line and an inverted control line, said normal control line being connected to a first control input of the corresponding transmission gates and said inverted control line being connected to a second inverted control input of said transmission gates.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-05-09 | 1986-11-08 | 1987-05-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-05-09 | 1990-11-08 | 1991-05-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-05-09 | 1994-11-08 | 1995-05-10 | $7700.00 | Window Closed / Lapsed |