High capacity secure address loop network

Claim 2

A loop switching system comprising, clockwise and counterclockwise transmission loop paths, common control means for defining recurrent frames of multi-bit time slots on each of said paths, and a plurality of ports disposed between said transmission paths, each of said ports having means for selectively reading and altering the bits of said time slots on both of said paths, including means for recognizing an idle time slot traversing one of said transmission paths, and means for seizing an idle slot for use on a connection to another of said ports including means controlled by said recognizing means at one said port for first marking busy an identifying bit in said idle time slot on said one of said transmission paths and for thereafter marking the identifying bit of the corresponding time slot on the other of said transmission paths.

Claim 3

The invention of claim 1 wherein said means controlled by said recognizing means includes means operative at the side of said port which is upstream on one of said buses when said port is a time slot requesting port for inserting an assignment word in said idle time slot and means operative at the side of said port which is downstream on one of said buses when said port is a time slot requesting port for recognizing the appearance of said assignment word and for thereafter marking said identifying bit busy.

Claim 4

The invention of claim 2 wherein each of said ports includes assigned time slot counter means and means controlled by said assigned time slot counter means at a port intermediate said one and said another of said time slot requesting ports for disregarding said assignment word and seizing said time slot identified by said counter means.

Claim 5

A loop switching system comprising, clockwise and counterclockwise transmission loop paths, common control means for defining recurrent frames of multi-bit time slots on each of said paths, each of said time slots having a control bit position and a plurality of data bit positions, a plurality of ports disposed between said transmission paths, each of said ports having means for selectively reading and altering the bits of said time slots on both of said paths, said common control means further including means for identifying a control bit position of a first of said time slots on one of said paths, and each of said ports further including means for counting the number of data bit positions intervening on said one of said paths between the arrival of said identified control bit position and the arrival of the control bit position of a time slot on the other of said paths.

Claim 6

A loop switching system comprising, clockwise and counterclockwise transmission loop paths, common control means for defining recurrent frames of multi-bit time slots on each of said paths, each of said time slots having a control bit position and a plurality of data bit positions, a plurality of ports disposed between said transmission paths, each of said ports having means for selectively reading and altering the bits of said time slots on both of said paths, said common control means further including means for identifying a control bit position of a first of said time slots on one of said paths, and each of said ports further including means for counting the number of data bit positions intervening on said one of said paths between the arrival of said identified control bit position and the arrival of the control bit position of a time slot on the other of said paths.

Claim 7

A loop switching system according to claim 4 wherein each of said ports includes means for registering said number of intervening bit positions and means for encoding said registered number in the control bit position of ensuing time slot words on both said paths.

Claim 8

A loop switching system according to claim 5 each of said ports further including means responsive to the service-requesting state of said port for both overwriting said identified control bit position upon its arrival at said port and for marking the control bit position of a subsequently arriving time slot on the other of said paths.

Claim 9

A loop switching system according to claim 6 wherein said common control means further includes means for transmitting over said paths an encoded sequence of control bit positions to identify the registered number of one of said ports.

Claim 10

A loop switching system comprising clockwise and counterclockwise transmission loop paths, common control means for defining recurrent frames of multi-bit time slots on each of said paths, each of said time slots having a control bit position and a plurality of data bit positions, a plurality of ports disposed between said transmission paths, each of said ports having means for selectively reading and altering the bits of said time slots on said paths, said common control means further including means for identifying a control bit position of a first of said time slots on one of said paths, and each of said ports further including means responsive to the service-requesting state of said port for both overwriting said identified control bit position upon its arrival at said port and for marking the control bit position of a subsequently arriving time slot on the other of said paths.

Claim 11

A loop switching system comprising clockwise and counterclockwise transmission loop paths, common control means for defining recurrent frames of multi-bit time slots on each of said paths, each of said time slots having a control bit position and a plurality of data bit positions, a plurality of ports disposed between said transmission paths, each of said ports having means for selectively reading and altering the bits of said time slots on said paths, said common control means further including means for identifying a control bit position of a first of said time slots on one of said paths, and each of said ports further including means responsive to the service-requesting state of said port for both overwriting said identified control bit position upon its arrival at said port and for marking the control bit position of a subsequently arriving time slot on the other of said paths.

Claim 12

A loop switching system according to claim 8 wherein said common control means includes means responsive to the difference in return times of said overwritten and said marked control bits for according said service-requesting one of said ports controlling access to said common control means.

Claim 13

A loop communication system comprising a pair of communication loops, a common control and a plurality of port circuits connected to each of said loops, said common control defining recurrent frames of plural bit time slot pulses traversing said loops in opposite directions; means for defining a first time slot and a first bit of each time slot in each of said directions as a control time slot and a control bit, respectively; and means responsive to the service requesting state of a first one of said port circuits for identifying said service requesting port to said common control, said responsive means including means for altering a bit of said control time slot traversing one of said loops and for altering the next traversing control bit on the other of said loops.

Claim 14

A loop communication system comprising a pair of communication loops, a common control and a plurality of port circuits connected to each of said loops, said common control defining recurrent frames of plural bit time slot pulses traversing said loops in opposite directions; means for defining a first time slot and a first bit of each time slot in each of said directions as a control time slot and a control bit, respectively; and means responsive to the service requesting state of a first one of said port circuits for identifying said service requesting port to said common control, said responsive means including means for altering a bit of said control time slot traversing one of said loops and for altering the next traversing control bit on the other of said loops.

Claim 15

A loop communication system according to claim 10 wherein said common control includes means for registering the times of arrival at said common control of said altered bit traversing each of said loops.

Claim 16

A loop communication system according to claim 10 wherein said responsive means includes: means for identifying the time slot bit arriving at said service-requesting port circuits on said one of said loops when said next traversing one of said control bit arrives on said other of said loops.

Claim 17

A loop communications system according to claim 12 wherein said responsive means includes means for encoding a sequence of subsequently arriving control bits with the number of said time slot bit arriving at said service-requesting port.

Claim 18

A variable bandwidth communications network comprising: a pair of digital transmission lines for carrying digital signals in reciprocal directions, a plurality of ports disposed along said pair of digital transmission lines, pairs of some of said ports being in a busy state and other pairs of said ports being in a service-requesting state, means for defining recurrent frames of plural bit time slots for each of said reciprocal directions, means at each downstream port of each busy pair of said ports using one of said time slots in each of said directions for marking said one of said time slots as idle, means at each upstream one of each pair of said service-requesting ports for marking said idle time slots as assignable for use on a call to a downstream one of said pair of service-requesting ports, and means at each downstream one of said pair of service-requesting ports for recognizing the arrival of said assignable time slots, and for seizing at least one of said assignable time slots for use.

Claim 19

A variable bandwidth communications network comprising: a pair of digital transmission lines for carrying digital signals in reciprocal directions, a plurality of ports disposed along said pair of digital transmission lines, pairs of some of said ports being in a busy state and other pairs of said ports being in a service-requesting state, means for defining recurrent frames of plural bit time slots for each of said reciprocal directions, means at each downstream port of each busy pair of said ports using one of said time slots in each of said directions for marking said one of said time slots as idle, means at each upstream one of each pair of said service-requesting ports for marking said idle time slots as assignable for use on a call to a downstream one of said pair of service-requesting ports, and means at each downstream one of said pair of service-requesting ports for recognizing the arrival of said assignable time slots, and for seizing at least one of said assignable time slots for use.

Claim 20

A variable bandwidth newtork according to claim 14 wherein said means for recognizing includes means for detecting said arrival of said assignable time slots on one of said pair of transmission lines and for marking the corresponding time slot on the other of said pair of transmission lines.

Claim 21

In a network having a plurality of ports disposed along a pair of digital transmission line buses over which respective, recurrent frames of plural bit time slots are defined, apparatus for seizing a pair of corresponding by numbered time slots appearing at one of said ports, comprising: a counter at each of said ports respective to each of said buses, means for normally incrementing each said counter to count said plural bit time slots of a respective one of said buses and for normally resetting said counter after counting a frame of said plural bit time slots, means operative incident to the commencement of a search for an assignable time slot for inhibiting the incrementing of each said counter, and means operative when an assignable time slot has been found on one of said buses for resetting the counter respective to one of said buses and for disabling said inhibiting means from inhibiting said normal incrementing of said counter respective to the other of said buses.

Claim 22

In a network having a plurality of ports disposed along a pair of digital transmission line buses over which respective, recurrent frames of plural bit time slots are defined, apparatus for seizing a pair of corresponding by numbered time slots appearing at one of said ports, comprising: a counter at each of said ports respective to each of said buses, means for normally incrementing each said counter to count said plural bit time slots of a respective one of said buses and for normally resetting said counter after counting a frame of said plural bit time slots, means operative incident to the commencement of a search for an assignable time slot for inhibiting the incrementing of each said counter, and means operative when an assignable time slot has been found on one of said buses for resetting the counter respective to one of said buses and for disabling said inhibiting means from inhibiting said normal incrementing of said counter respective to the other of said buses.

Claim 23

In a network according to claim 16, the combination wherein said means operative when said assignable time slot has been found includes means for marking a corresponding time slot bit on each of said buses when said respective counter is reset.

Claim 24

A network comprising: a pair of digital transmission line buses over which respective recurrent frames of plural bit time slot signals are transported, a plurality of ports disposed along said buses, control means at each of said ports for employing one of said buses as a receiving side bus and the other of said buses as a transmitting side bus for said time slot signals, counter means at said ports respective to said transmitting side and said receiving side buses, each of said counters becoming reset after a count equaling a complete frame of said plural bit time slot signals, means operative at one of said ports incident to the detection of an assignable time slot on said receiving side bus for resetting both said respective counter means and for connecting both said counters to be incremented by said time slot signals appearing on said receiving side bus, means responsive to the end of one of said recurrent frames appearing on said receiving side bus for stopping one of said counters, and means responsive to the start of one of said recurrent frames appearing in said transmitting side bus for said stopped one of said counters to be incremented by said time slot signals appearing on said transmitting side bus.

Claim 25

A network comprising: a pair of digital transmission line buses over which respective recurrent frames of plural bit time slot signals are transported, a plurality of ports disposed along said buses, control means at each of said ports for employing one of said buses as a receiving side bus and the other of said buses as a transmitting side bus for said time slot signals, counter means at said ports respective to said transmitting side and said receiving side buses, each of said counters becoming reset after a count equaling a complete frame of said plural bit time slot signals, means operative at one of said ports incident to the detection of an assignable time slot on said receiving side bus for resetting both said respective counter means and for connecting both said counters to be incremented by said time slot signals appearing on said receiving side bus, means responsive to the end of one of said recurrent frames appearing on said receiving side bus for stopping one of said counters, and means responsive to the start of one of said recurrent frames appearing in said transmitting side bus for said stopped one of said counters to be incremented by said time slot signals appearing on said transmitting side bus.

Claim 26

A loop switching network comprising a plurality of ports each adapted to receive, store and transmit digital signals, first loop means for conveying said digital signals between said ports in a first direction, second loop means for conveying said digital signals between said ports in a direction opposite to said first direction, clock means defining a repetitive sequence of time slots respective to said first and second loop means, each of said time slots including a plurality of bit intervals, means for defining in each of said time slots a control bit position, each of said ports including means for detecting the arrival of said control bit position on each of said loop means, and means for selectively comparing the contents of said control bit positions arriving over each of said loop means.

Claim 27

A loop switching network comprising a plurality of ports each adapted to receive, store and transmit digital signals, first loop means for conveying said digital signals between said ports in a first direction, second loop means for conveying said digital signals between said ports in a direction opposite to said first direction, clock means defining a repetitive sequence of time slots respective to said first and second loop means, each of said time slots including a plurality of bit intervals, means for defining in each of said time slots a control bit position, each of said ports including means for detecting the arrival of said control bit position on each of said loop means, and means for selectively comparing the contents of said control bit positions arriving over each of said loop means.

Claim 28

A loop network according to claim 19 including means for identifying the time slot bit interval obtaining on said first loop means at one of said port circuits when said control bit position arrives on said second loop means at said one of said ports.

Claim 29

A loop network according to claim 20 further including means controlled by said comparing means for receiving an encoded sequence of signals in the control bit position of successive ones of said time slots.

Claim 30

A loop switching network according to claim 20 wherein each of said ports includes input encoder and output decoder means, means for separately summing a digital signal arriving over said first loop means with the output of said input encoding means, means for separately summing said output of said encoding means with said digital signal arriving over said second loop means, and third means for separately summing said digital signals arriving over first and said second loop means and delivering the result to said output decoder means.

Claim 31

A loop network according to claim 22 further comprising means for activating said first means for separately summing and said second means for separately summing when a corresponding time slot appears at said port on said first and said second loop means.

Claim 32

A loop switching network according to claim 20 further comprising means for assigning to a service requesting pair of said ports an idle time slot occupying a corresponding position in said sequence on said first and said second loop means whereby one of said first and said second loop means whereby one of said pair of ports transmits digital signals to the other of said pair in said time slot over said first loop means and receives digital signals transmitted by said other of said pair in said time slot over said second loop means.

Claim 33

A switching network comprising a plurality of port circuits, loop means for transporting digital signals fromm a calling one of said port circuits serially through intermediate ones of said port circuits to a called one of said port circuits, and clock means for defining recurrent sequences of time slots in which said digital signal are carried Characterized in that said loop means includes a transmission path for carrying said signals in opposite directions and wherein said clock means defines correspondingly numbered sequences of time slots exhibiting distinctive relative arrival times for each of said directions at said port circuits.

Claim 34

A switching network comprising a plurality of port circuits, loop means for transporting digital signals fromm a calling one of said port circuits serially through intermediate ones of said port circuits to a called one of said port circuits, and clock means for defining recurrent sequences of time slots in which said digital signal are carried Characterized in that said loop means includes a transmission path for carrying said signals in opposite directions and wherein said clock means defines correspondingly numbered sequences of time slots exhibiting distinctive relative arrival times for each of said directions at said port circuits.

Claim 35

A switching network according to claim 25 wherein said time slots each defines a plurality of bit intervals, further characterized in that said transmission path carrying said signals includes means for separating each of said signals includes means for separating each of said port circuits from its adjacent port circuit in said opposite directions by at least one of said bit intervals.

Claim 36

A switching network according to claim 26 further characterized in that one of said port circuits in a common control port, said common control port including means for addressing any of the remaining plurality of said port circuits by marking a predetermined bit position of one of said time slots in one of said directions and a plurality of said predetermined bit positions of a succession of said time slots in the other of said directions.

Claim 37

A switching network according to claim 26 further characterized in that each of said port circuits includes means for receiving a marked addressing bit in said predetermined bit position over said transmission path in each of said opposite directions.

Claim 38

A switching network according to claim 28 further characterized in that said addressing bit receiving means includes means for storing a plurality of addressing bits arriving in one of said directions until the arrival of said succession of addressing bits from said other of said directions.

Claim 39

A switching network according to claim 29, further characterized in that said receiving means includes means for comparing said addressing bits arriving in said one of said directions with said addressing bits arriving in the other of said directions.

Claim 40

A loop switching system comprising: a plurality of ports including a common control port and a pair of buses linking all of said ports and carrying digital signals in opposite directions between different pairs of said ports, means for defining repetitive intervals for assigning said digital signals into time slots, and means for addressing any of said ports according to the difference in propagation times taken by a pair of said digital signals transmitted over said buses.

Claim 41

A loop switching system comprising: a plurality of ports including a common control port and a pair of buses linking all of said ports and carrying digital signals in opposite directions between different pairs of said ports, means for defining repetitive intervals for assigning said digital signals into time slots, and means for addressing any of said ports according to the difference in propagation times taken by a pair of said digital signals transmitted over said buses.

Claim 42

A loop switching system according to claim 31 wherein said means for defining said repetitive intervals includes means for assigning predetermined bit positions of said time slots as data bit positions and a first bit position of each of said time slots as a control bit position and wherein said means for addressing includes means for marking a control bit position of one of said time slots on each of said buses.

Claim 43

A loop switching system comprising: a plurality of ports including a common control port and a pair of buses linking all of said ports and carrying digital signals in opposite directions between different pairs of said ports, means for defining a plurality of different kinds of frames, each consisting of the same number of plural bit time slots, said frames differing from each other solely in the significance attributable to the first bit of each of said time slots, and means for assigning different data words to the remaining bit positions of each of said time slots of any of said frames.

Claim 44

A loop switching system comprising: a plurality of ports including a common control port and a pair of buses linking all of said ports and carrying digital signals in opposite directions between different pairs of said ports, means for defining a plurality of different kinds of frames, each consisting of the same number of plural bit time slots, said frames differing from each other solely in the significance attributable to the first bit of each of said time slots, and means for assigning different data words to the remaining bit positions of each of said time slots of any of said frames.

Claim 45

A loop switching system according to claim 33 wherein said addressing means includes means for marking a single predetermined bit of one of said time slots of each of said buses.

Claim 46

A loop switching system according to claim 34 wherein said addressing means includes means at each of said ports for counting the number of bit intervals intervening between the arrival at said port of said single bit on each of said buses.

Claim 47

A loop switching system according to claim 35 wherein said addressing means includes means at each of said ports controlled by said counting means for registering said number of bit intervals and wherein said port further comprises means for encoding said registered number and for transmitting said number to said common control.

Claim 48

A port for a loop switching system having clockwise and counterclockwise loop transmission paths, comprising means for identifying time slot sequences on each of said paths, and means controlled by said identifying means for responding to the arrival within a predetermined interval of corresponding sequences on each of said paths.

Claim 49

A port for a loop switching system having clockwise and counterclockwise loop transmission paths, comprising means for identifying time slot sequences on each of said paths, and means controlled by said identifying means for responding to the arrival within a predetermined interval of corresponding sequences on each of said paths.

Claim 50

A port circuit according to claim 37 further including means for identifying the appearance of a control bit position in a time slot on each of said paths, and means for responding to the difference in arrival times of said control bit position on each of said paths.

Claim 51

A port circuit according to claim 37 further including means for selectively overwriting said identifying control bit positions on said paths.