Delay circuit used in semiconductor memory device

Claim 1

A delay circuit for providing a small increment of delay comprising: a series insulated-gate field-effect transistor having a source-to-drain current path and a gate electrode, the current path of said series transistor being connected in series between an input terminal and an output terminal; a precharge circuit having an insulated-gate field-effect transistor for precharging said gate electrode of said series transistor to a voltage level, said precharge transistor having a source-to-drain current path and a gate, said gate electrode of the series transistor being connected to a constant supply voltage through the source-to-drain path of the precharge transistor; means for applying an input voltage to the input terminal, the input voltage having a given transition from one level to another; a capacitance means connected between said output terminal and said gate electrode of the series transistor, the capacitance means being much larger than the inherent parasitic capacitance at the gate electrode of the series transistor and functioning for boosting the voltage on said gate electrode of the series transistor at said given transition by coupling from the output terminal to the gate electrode of the series transistor; wherein the primary electrical path between said input terminal and said output terminal for generating an output representation of said given transition is via said source-to-drain path of said series transistor, and wherein a third transistor connects said output terminal to ground, the third transistor having a gate connected to a precharge circuit to be precharged prior to said transition in order to hold the output terminal at ground at the beginning of said given transistion.