Semiconductor memory circuit

Claim 2

A semiconductor memory circuit which comprises: at least one memory cell; at least one word line; at least one data line segment, only a single data line segment being provided for each memory cell; and at least one control voltage line whose potential is set at one of different levels in accordance with a selected operation mode; said at least one memory cell including a first MOS transistor whose source is connected to said control voltage line, a second MOS transistor whose gate and drain are connected to the drain and gate of said first MOS transistor and whose source is connected to said control voltage line, first and second load resistive means respectively connected to the drains of said first and second MOS transistors, and a third MOS transistor whose gate is connected to said word line, and whose current path is connected between the drain of said first MOS transistor and said data line segment, the drains of said first and second MOS transistors being connected to a power supply terminal impressed with a high voltage through the corresponding first and second load resistive means, and said at least one control voltage line being held at a high voltage for a predetermined period of time in the write mode and set at a low voltage during the read mode.

Claim 3

A semiconductor memory circuit according to claim 1, wherein said first and second load resistive means are formed of MOS transistors.

Claim 4

A semiconductor memory circuit according to claim 1, wherein said first and second load resistive means are respectively formed of a polycrystalline silicon layer.

Claim 5

A semiconductor memory circuit which comprises: a plurality of matrix-arranged memory cells, each of said memory cells including a first MOS transistor, a second MOS transistor whose source, drain and gate are respectively connected to the source, gate and drain of said first MOS transistor, first and second load resistive means respectively connected to the drains of said first and second MOS transistors, and a third MOS transistor whose current path is connected at one end to the drain of said first MOS transistor; a plurality of word lines, each of said word lines being connected in common to the gate of the third MOS transistor of each respective memory cell arranged in the same row; a plurality of data lines, only a single data line being provided for those memory cells which are arranged in the same column and each of said plurality of data lines being connected in common to the other end of the current path of each of the third MOS transistors of the respective memory cells arranged in the same column; and a plurality of control voltage lines, each of said control voltage lines being connected in common to the sources of said first and second MOS transistors of the respective memory cells arranged in the same column, the potential of each control voltage line being set at one of different levels in accordance with a selected operation mode, the drains of said first and second MOS transistors of each of said memory cells being connected to a power supply terminal impressed with a high voltage through the corresponding first and second resistive means, and said at least one control voltage line being held at a high voltage for a predetermined period of time in the write mode and set at a low voltage during the read mode.

Claim 6

A semiconductor memory circuit which comprises: a plurality of matrix-arranged memory cells, each of said memory cells including a first MOS transistor, a second MOS transistor whose source, drain and gate are respectively connected to the source, gate and drain of said first MOS transistor, first and second load resistive means respectively connected to the drains of said first and second MOS transistors, and a third MOS transistor whose current path is connected at one end to the drain of said first MOS transistor; a plurality of word lines, each of said word lines being connected in common to the gate of the third MOS transistor of each respective memory cell arranged in the same row; a plurality of data lines, only a single data line being provided for those memory cells which are arranged in the same column and each of said plurality of data lines being connected in common to the other end of the current path of each of the third MOS transistors of the respective memory cells arranged in the same column; and a plurality of control voltage lines, each of said control voltage lines being connected in common to the sources of said first and second MOS transistors of the respective memory cells arranged in the same column, the potential of each control voltage line being set at one of different levels in accordance with a selected operation mode, the drains of said first and second MOS transistors of each of said memory cells being connected to a power supply terminal impressed with a high voltage through the corresponding first and second resistive means, and said at least one control voltage line being held at a high voltage for a predetermined period of time in the write mode and set at a low voltage during the read mode.

Claim 7

A semiconductor memory circuit according to claim 4, wherein said first and second load resistive means are formed of MOS transistors.

Claim 8

A semiconductor memory circuit according to claim 4, wherein said first and second load resistive means are respectively formed of a polycrystalline silicon layer.