Distributed signal processing system

Claim 2

In combination: a plurality of distributed signal processing systems; each of said systems comprising a plurality of elements including a signal processor, a mass memory, and an input-output controller, and a first bus means for interconnecting in common said plurality of elements; said input-output controller of each one of said systems comprising a second bus means for interconnecting a plurality of said systems by coupling said second bus means to said first bus means of another of said systems and for providing coupling to a plurality of input-output data devices; and each of said elements comprising one or more bus transceivers and arbitration means coupled to one of said first and second bus means for determining the one of a plurality of elements connected to said one of the first and second bus means that obtains first use of said connected one of the first and second bus means when more than one of said elements attempt to use one of said first and second bus means simultaneously.

Claim 3

The combination as recited in claim 1 wherein: each of said elements in each of said systems comprises means for detecting a faulty element.

Claim 4

The combination as recited in claim 2 wherein: at least one of said elements in said systems comprises means for performing self-repair of said systems when said faulty element is detected.

Claim 5

The combination as recited in claim 1 wherein: said first bus means for interconnecting said plurality of elements further comprises at least two identical buses for fault-tolerant operation capability.

Claim 6

The combination as recited in claim 1 wherein: said second bus means further comprises at least two identical buses for fault-tolerant operation capability.

Claim 7

The combination as recited in claim 1 wherein: said input-output controller comprises a plurality of operating modes which includes a bus extended mode for communicating with said interconnected systems.

Claim 8

The combination as recited in claim 6 wherein: said input-output controller further comprises a dynamic input-output mode for communicating with said input-output data devices.

Claim 9

In combination: a plurality of distributed signal processing systems; each of said systems comprising a plurality of elements including a signal processor, a mass memory and an input-output controller, and a first bus means for interconnecting in common said plurality of elements; said input-output controller of each one of said systems comprising a second bus means for interconnecting a plurality of said systems by coupling said second bus means to said first bus means of another of said systems and for providing coupling to a plurality of input-output data devices; each of said elements comprising one or more bus transceivers and arbitration means coupled to one of said first and second bus means for determining the one of a plurality of elements connected to said one of the first and second bus means that obtains first use of said connected one of the first and second bus means when more than one of said elements attempt to use one of said first and second bus means simultaneously; and said signal processor comprising operating means for managing processing tasks within said plurality of elements and systems.

Claim 10

In combination: a plurality of distributed signal processing systems; each of said systems comprising a plurality of elements including a signal processor, a mass memory and an input-output controller, and a first bus means for interconnecting in common said plurality of elements; said input-output controller of each one of said systems comprising a second bus means for interconnecting a plurality of said systems by coupling said second bus means to said first bus means of another of said systems and for providing coupling to a plurality of input-output data devices; each of said elements comprising one or more bus transceivers and arbitration means coupled to one of said first and second bus means for determining the one of a plurality of elements connected to said one of the first and second bus means that obtains first use of said connected one of the first and second bus means when more than one of said elements attempt to use one of said first and second bus means simultaneously; and said signal processor comprising operating means for managing processing tasks within said plurality of elements and systems.

Claim 11

The combination as recited in claim 8 wherein: each of said elements in each of said systems comprises means for detecting a faulty element.

Claim 12

The combination as recited in claim 9 wherein: at least one of said elements in said systems comprises means for performing self-repair of said systems when said faulty element is detected.

Claim 13

The combination as recited in claim 8 wherein: said first bus means for interconnecting said plurality of elements further comprises at least two identical buses for fault-tolerant operation capability.

Claim 14

The combination as recited in claim 8 wherein: said second bus means further comprises at least two identical buses for fault-tolerant operation capability.

Claim 15

A combination as recited in claim 8 wherein: said input-output controller comprises a plurality of operating modes which includes a bus extended mode for communicating with said interconnected systems.

Claim 16

The combination as recited in claim 13 wherein: said input-output controller further comprises a dynamic input-output mode for communicating with said input-output data devices.

Claim 17

In combination: a plurality of distributed signal processing systems; each of said systems comprising a plurality of elements including a plurality of signal processors, a plurality of mass memories and a plurality of input-output controllers for fault-tolerant operation capability, and a first bus means for interconnecting in common said plurality of elements; each one of said input-output controllers comprising a second bus means for interconnecting a plurality of said systems by coupling said second bus means of one of said systems to said first bus means of another of said systems and for providing coupling to a plurality of input-output data devices; and each of said elements comprising one or more bus transceivers and arbitration means coupled to one of said first and second bus means for determining the one of a plurality of elements connected to said one of the first and second bus means that obtains first use of said connected one of the first and second bus means when more than one of said elements attempt to use one of said first and second bus means simultaneously.

Claim 18

In combination: a plurality of distributed signal processing systems; each of said systems comprising a plurality of elements including a plurality of signal processors, a plurality of mass memories and a plurality of input-output controllers for fault-tolerant operation capability, and a first bus means for interconnecting in common said plurality of elements; each one of said input-output controllers comprising a second bus means for interconnecting a plurality of said systems by coupling said second bus means of one of said systems to said first bus means of another of said systems and for providing coupling to a plurality of input-output data devices; and each of said elements comprising one or more bus transceivers and arbitration means coupled to one of said first and second bus means for determining the one of a plurality of elements connected to said one of the first and second bus means that obtains first use of said connected one of the first and second bus means when more than one of said elements attempt to use one of said first and second bus means simultaneously.

Claim 19

The combination as recited in claim 15 wherein: each of said elements in each of said systems comprises means for detecting a faulty element.

Claim 20

The combination as recited in claim 16 wherein: at least one of said elements in said systems comprises means for performing self-repair of said systems when said faulty element is detected.

Claim 21

The combination as recited in claim 15 wherein: said first bus means for interconnecting said plurality of elements further comprises at least two identical buses for fault-tolerant operation capability.

Claim 22

The combination as recited in claim 15 wherein: said second bus means further comprises at least two identical buses for fault-tolerant operation capability.

Claim 23

The combination as recited in claim 9 wherein: each of said input-output controllers comprises a plurality of operating modes which includes a bus extended mode for communicating with said interconnected systems.

Claim 24

The combination as recited in claim 20 wherein: each of said input-output controllers further comprises a dynamic input-output mode for communicating with said input-output data devices.

Claim 25

In combination: a plurality of distributed signal processing systems; each of said systems comprising a plurality of elements including a plurality of signal processors, a plurality of mass memories and a plurality of input-output controllers for fault-tolerant operation capability, and a first bus means for interconnecting in common said plurality of elements; each one of said input-output controllers comprising a second bus means for interconnecting a plurality of said systems by coupling said second bus means of one of said systems to said first bus means of another of said systems and for providing coupling to a plurality of input-output data devices; each of said elements comprising one or more bus transceivers and arbitration means coupled to one of said first and second bus means for determining the one of a plurality of elements connected to said one of the first and second bus means that obtains first use of said connected one of the first and second bus means when more than one of said elements attempt to use one of said first and second bus means simultaneously; each of said elements comprising means for detecting a faulty element; and self-repair means for correcting said faulty element by removing said faulty element from operating service and replacing said faulty element with a similar spare element.

Claim 26

In combination: a plurality of distributed signal processing systems; each of said systems comprising a plurality of elements including a plurality of signal processors, a plurality of mass memories and a plurality of input-output controllers for fault-tolerant operation capability, and a first bus means for interconnecting in common said plurality of elements; each one of said input-output controllers comprising a second bus means for interconnecting a plurality of said systems by coupling said second bus means of one of said systems to said first bus means of another of said systems and for providing coupling to a plurality of input-output data devices; each of said elements comprising one or more bus transceivers and arbitration means coupled to one of said first and second bus means for determining the one of a plurality of elements connected to said one of the first and second bus means that obtains first use of said connected one of the first and second bus means when more than one of said elements attempt to use one of said first and second bus means simultaneously; each of said elements comprising means for detecting a faulty element; and self-repair means for correcting said faulty element by removing said faulty element from operating service and replacing said faulty element with a similar spare element.

Claim 27

The combination as recited in claim 22 wherein: said self-repair means comprises means for changing an address of a spare element to an address of said faulty element.

Claim 28

The combination as recited in claim 22 wherein: said first bus means for interconnecting said plurality of elements further comprises at least two identical buses for fault-tolerant operation capability.

Claim 29

The combination as recited in claim 22 wherein: said second bus means further comprises at least two identical buses for fault-tolerant operation capability.

Claim 30

The combination as recited in claim 22 wherein: each of said input-output controllers comprises a plurality of operating modes which includes a bus extended mode for communicating with said interconnected systems.

Claim 31

The combination as recited in claim 26 wherein: each of said input-output controllers further comprises a dynamic input-output mode for communicating with said input-output data devices.

Claim 32

In combination: a plurality of distributed signal processing systems; each of said systems comprising a plurality of elements including a plurality of signal processors, a plurality of mass memories and a plurality of input-output controllers for fault-tolerant operation capability, and a first bus means for interconnecting in common said plurality of elements; each one of said input-output controllers comprising a second bus means for interconnecting a plurality of said systems and by coupling said second bus means of one of said systems to said first bus means of another of said systems and for providing coupling to a plurality of input-output data devices; each of said elements comprising one or more bus transceivers and arbitration means coupled to one of said first and second bus means for determining the one of a plurality of elements connected to said one of the first and second bus means that obtains first use of said connected one of the first and second bus means when more than one of said elements attempt to use one of said first and second bus means simultaneously; each of said elements comprising means for detecting a faulty element; self-repair means comprising an element address register in each of said elements for removing said detected faulty element from operating service and replacing said faulty element with a spare element; and said signal processors comprising distributed operating system means for managing processing tasks and self-repair means within said plurality of elements and systems.

Claim 33

In combination: a plurality of distributed signal processing systems; each of said systems comprising a plurality of elements including a plurality of signal processors, a plurality of mass memories and a plurality of input-output controllers for fault-tolerant operation capability, and a first bus means for interconnecting in common said plurality of elements; each one of said input-output controllers comprising a second bus means for interconnecting a plurality of said systems and by coupling said second bus means of one of said systems to said first bus means of another of said systems and for providing coupling to a plurality of input-output data devices; each of said elements comprising one or more bus transceivers and arbitration means coupled to one of said first and second bus means for determining the one of a plurality of elements connected to said one of the first and second bus means that obtains first use of said connected one of the first and second bus means when more than one of said elements attempt to use one of said first and second bus means simultaneously; each of said elements comprising means for detecting a faulty element; self-repair means comprising an element address register in each of said elements for removing said detected faulty element from operating service and replacing said faulty element with a spare element; and said signal processors comprising distributed operating system means for managing processing tasks and self-repair means within said plurality of elements and systems.

Claim 34

The combination as recited in claim 28 wherein: said first bus means for interconnecting said plurality of elements further comprises redundant busses for fault-tolerant operation capability.

Claim 35

The combination as recited in claim 29 wherein: said second bus means for interconnecting a plurality of said systems further comprises at least two identical buses for fault-tolerant operation capability.

Claim 36

The combination as recited in claim 28 wherein: said plurality of elements, first bus means, second bus means and said self-repairing means in each of said distributed signal processing systems provide an operating capability in the presence of one or more faults in said systems.

Claim 37

The combination as recited in claim 28 wherein: said removal of said detected faulty element is accomplished by changing an address in said element address register of said spare element to an address of said faulty element.

Claim 38

The combination as recited in claim 28 wherein: said self-repair means in each of said distributed signal processing systems performs said self-repair without element or system redesign by changing said element address in said element register causing an element to be added or deleted from said operating service.

Claim 39

The combination as recited in claim 28 wherein: each of said input-output controllers comprises a plurality of operating modes which includes a bus extended mode for communicating with said interconnected systems.

Claim 40

The combination as recited in claim 34 wherein: each of said input-output controllers further comprises a dynamic input-output mode for communicating with said input-output data devices.

Claim 41

In combination: a plurality of distributed signal processing systems; each of said systems comprising a plurality of elements including a plurality of signal processors, a plurality of mass memories and a plurality of input-output controllers for fault-tolerant operation capability, and a first bus means for interconnecting in common said plurality of elements; each one of said input-output controllers comprising a second bus means for interconnecting a plurality of said systems by coupling said second bus means of one of said systems to said first bus means of another of said systems and for providing coupling of a plurality of input-output data devices; each of said elements comprising one or more bus transceivers and arbitration means coupled to one of said first and second bus means for determining the one of a plurality of elements connected to said one of the first and second bus means that obtains first use of said connected one of the first and second bus means when more than one of said elements attempt to use one of said first and second bus means simultaneously; each of said elements comprising means for detecting a faulty element; self-repair means comprising an element address register in each of said elements for removing said detected faulty element from operating service and replacing said faulty element with a spare element; and a distributed operating system means in said signal processors for managing said plurality of elements comprising a local level segment of said distributed operating system, DOS-0, for performing individual signal processor management and fault monitoring, and a system level segment of said distributed operating system, DOS-1, for performing system task management, fault monitoring and self-repair.

Claim 42

In combination: a plurality of distributed signal processing systems; each of said systems comprising a plurality of elements including a plurality of signal processors, a plurality of mass memories and a plurality of input-output controllers for fault-tolerant operation capability, and a first bus means for interconnecting in common said plurality of elements; each one of said input-output controllers comprising a second bus means for interconnecting a plurality of said systems by coupling said second bus means of one of said systems to said first bus means of another of said systems and for providing coupling of a plurality of input-output data devices; each of said elements comprising one or more bus transceivers and arbitration means coupled to one of said first and second bus means for determining the one of a plurality of elements connected to said one of the first and second bus means that obtains first use of said connected one of the first and second bus means when more than one of said elements attempt to use one of said first and second bus means simultaneously; each of said elements comprising means for detecting a faulty element; self-repair means comprising an element address register in each of said elements for removing said detected faulty element from operating service and replacing said faulty element with a spare element; and a distributed operating system means in said signal processors for managing said plurality of elements comprising a local level segment of said distributed operating system, DOS-0, for performing individual signal processor management and fault monitoring, and a system level segment of said distributed operating system, DOS-1, for performing system task management, fault monitoring and self-repair.

Claim 43

The combination as recited in claim 36 wherein: said local level segment, DOS-0, of said distributed operating system comprises identical ROMS located in each of said signal processors.

Claim 44

The combination as recited in claim 36 wherein: said first bus means for interconnecting said plurality of elements further comprises two identical busses for fault-tolerant operation capability.

Claim 45

The combination as recited in claim 38 wherein: said second bus means for interconnecting a plurality of said systems further comprises at least two identical buses for fault-tolerant operation capability.

Claim 46

The combination as recited in claim 36 wherein: said plurality of elements, first bus means, second bus means and said self-repairing means in each of said distributed signal processing systems provide an operating capability in the presence of one or more faults in said system.

Claim 47

The combination as recited in claim 36 wherein: said removal of said detected faulty element is accomplished by changing an address in said element address register of said spare element to an address of said faulty element.

Claim 48

The combination as recited in claim 36 wherein: said self-repair means in each of said distributed signal processing systems self-repair without element or system redesign by changing said element address in said element address register causing elements to be added or deleted from operating service.

Claim 49

The combination as recited in claim 36 wherein: each of said input-output controllers comprises a plurality of operating modes which includes a bus extended mode for communicating with said interconnected systems.

Claim 50

The combination as recited in claim 43 wherein: each of said input-output controllers further comprises a dynamic input-output mode for communicating with said input-output data devices.

Claim 51

In combination: a plurality of distributed signal processing systems; each of said systems comprising a plurality of elements including a plurality of signal processors, a plurality of mass memories and a plurality of input-output controllers, and a first bus means for interconnecting in common said plurality of elements; each one of said input-output controllers comprising a second bus means for interconnecting a plurality of said systems by coupling said second bus means of one of said systems to said first bus means of another of said systems and for providing coupling to a plurality of input-output data devices; each of said elements comprising one or more bus transceivers and arbitration means coupled to one of said first and second bus means for determining the one of a plurality of elements connected to said one of the first and second bus means that obtains first use of said connected one of the first and second bus means when more than one of said elements attempt to use one of said first and second bus means simultaneously; each of said elements comprising means for detecting a faulty element; self-repair means comprising an element address register in each of said elements for removing said detected faulty element from operating service and replacing said faulty element with a spare element; said signal processors comprising distributed operating system means for managing processing tasks and self repair means within said plurality of elements and systems; and arithmetic means in each of said signal processors for performing multiplication and addition operations simultaneously within a single clock cycle time period of said signal processors.

Claim 52

In combination: a plurality of distributed signal processing systems; each of said systems comprising a plurality of elements including a plurality of signal processors, a plurality of mass memories and a plurality of input-output controllers, and a first bus means for interconnecting in common said plurality of elements; each one of said input-output controllers comprising a second bus means for interconnecting a plurality of said systems by coupling said second bus means of one of said systems to said first bus means of another of said systems and for providing coupling to a plurality of input-output data devices; each of said elements comprising one or more bus transceivers and arbitration means coupled to one of said first and second bus means for determining the one of a plurality of elements connected to said one of the first and second bus means that obtains first use of said connected one of the first and second bus means when more than one of said elements attempt to use one of said first and second bus means simultaneously; each of said elements comprising means for detecting a faulty element; self-repair means comprising an element address register in each of said elements for removing said detected faulty element from operating service and replacing said faulty element with a spare element; said signal processors comprising distributed operating system means for managing processing tasks and self repair means within said plurality of elements and systems; and arithmetic means in each of said signal processors for performing multiplication and addition operations simultaneously within a single clock cycle time period of said signal processors.

Claim 53

In combination: a plurality of distributed signal processing systems; each of said systems comprising a plurality of elements including a plurality of signal processors, a plurality of mass memories and a plurality of input-output controllers for fault tolerant operation capability, and a first bus means for interconnecting in common said plurality of elements; each one of said input-output controllers comprising a second bus means for interconnecting a plurality of said systems by coupling said second bus means of one of said systems to said first bus means of another of said systems and for providing coupling to a plurality of input-output data devices; each of said elements comprising one or more bus transceivers and arbitration means coupled to one of said first and second bus means for determining the one of a plurality of elements connected to said one of the first and second bus means that obtains first use of said connected one of the first and second bus means when more than one of said elements attempt to use one of said first and second bus means simultaneously; each of said elements comprising means for detecting a faulty element; self-repair means comprising an element address register in each of said elements for removing said detected faulty element from operating service and replacing said faulty element with a spare element; a distributed operating system means in said signal processors for managing said plurality of elements comprising a local level segment of said distributed operating system, DOS-0, for performing individual signal processor management and fault monitoring, and a system level segment of said distributed operating system, DOS-1, for performing system task management, fault monitoring and self-repair; OPERATE instruction means comprising instructions for performing control operations between an application program and said local level segment, DOS-0, of said distributed operating system, for performing complex signal processing operations including a multiplication of two complex matricies, and a radar target detection and clutter map update calculation and for performing logic and memory diagnostic tests.

Claim 54

In combination: a plurality of distributed signal processing systems; each of said systems comprising a plurality of elements including a plurality of signal processors, a plurality of mass memories and a plurality of input-output controllers for fault tolerant operation capability, and a first bus means for interconnecting in common said plurality of elements; each one of said input-output controllers comprising a second bus means for interconnecting a plurality of said systems by coupling said second bus means of one of said systems to said first bus means of another of said systems and for providing coupling to a plurality of input-output data devices; each of said elements comprising one or more bus transceivers and arbitration means coupled to one of said first and second bus means for determining the one of a plurality of elements connected to said one of the first and second bus means that obtains first use of said connected one of the first and second bus means when more than one of said elements attempt to use one of said first and second bus means simultaneously; each of said elements comprising means for detecting a faulty element; self-repair means comprising an element address register in each of said elements for removing said detected faulty element from operating service and replacing said faulty element with a spare element; a distributed operating system means in said signal processors for managing said plurality of elements comprising a local level segment of said distributed operating system, DOS-0, for performing individual signal processor management and fault monitoring, and a system level segment of said distributed operating system, DOS-1, for performing system task management, fault monitoring and self-repair; OPERATE instruction means comprising instructions for performing control operations between an application program and said local level segment, DOS-0, of said distributed operating system, for performing complex signal processing operations including a multiplication of two complex matricies, and a radar target detection and clutter map update calculation and for performing logic and memory diagnostic tests.

Claim 55

In a network comprising a plurality of distributed signal processing systems each of said systems comprising a plurality of elements, the method of determining which one of said elements becomes an executive containing a system level segment of a distributed operating system, DOS-1, comprising steps of: performing self-test programs located in a local level segment, DOS-0, of said distributed operating system in a signal processor when power is applied; sending a "ready and executive request" message from said signal processor to a mass memory after the successful completion of said self-test programs; performing bus arbitration if two or more of said signal processors try to use a bus simultaneously for sending said "ready and executive request" message; and preventing more than one signal processor from obtaining said executive of said distributed operating system, by changing the address of said mass memory as soon as said mass memory receives said first "ready and executive request" message resulting in said other signal processors entering an idle state until assigned a task by said executive.

Claim 56

In a network comprising a plurality of distributed signal processing systems each of said systems comprising a plurality of elements, the method of determining which one of said elements becomes an executive containing a system level segment of a distributed operating system, DOS-1, comprising steps of: performing self-test programs located in a local level segment, DOS-0, of said distributed operating system in a signal processor when power is applied; sending a "ready and executive request" message from said signal processor to a mass memory after the successful completion of said self-test programs; performing bus arbitration if two or more of said signal processors try to use a bus simultaneously for sending said "ready and executive request" message; and preventing more than one signal processor from obtaining said executive of said distributed operating system, by changing the address of said mass memory as soon as said mass memory receives said first "ready and executive request" message resulting in said other signal processors entering an idle state until assigned a task by said executive.

Claim 57

In combination a plurality of elements; said plurality of elements comprising a signal processor, a mass memory and an input-output controller; first bus means for interconnecting in common said plurality of elements to form a distributed signal processing system; a plurality of said distributed signal processing system forming a network comprising a second bus interconnecting means between said input-output controller of one of said systems and said first bus means of another of said systems; means for communicating between said systems by at least two separate busses; and said plurality of systems comprising means in at least one element for performing self-repair of said network.

Claim 58

In combination a plurality of elements; said plurality of elements comprising a signal processor, a mass memory and an input-output controller; first bus means for interconnecting in common said plurality of elements to form a distributed signal processing system; a plurality of said distributed signal processing system forming a network comprising a second bus interconnecting means between said input-output controller of one of said systems and said first bus means of another of said systems; means for communicating between said systems by at least two separate busses; and said plurality of systems comprising means in at least one element for performing self-repair of said network.

Claim 59

In combination: a plurality of elements; said plurality of elements comprising a signal processor, a mass memory and an input-output controller; first bus means for interconnecting in common said plurality of elements to form a distributed signal processing system; a plurality of said distributed signal processing systems forming a network comprising a second bus interconnecting means between said input-output controller of one of said systems and said first bus means of another of said systems; means for communicating between said systems by at least two separate busses; means for communicating with a plurality of input-output data devices by at least two separate busses; said plurality of systems comprising means in at least one element for performing self-repair of said network; and said input-output controller comprising a plurality of operating modes including a bus extended mode for communicating between said interconnected systems, and a dynamic input-output mode for communicating with said input-output data devices coupled to said controller.

Claim 60

In combination: a plurality of elements; said plurality of elements comprising a signal processor, a mass memory and an input-output controller; first bus means for interconnecting in common said plurality of elements to form a distributed signal processing system; a plurality of said distributed signal processing systems forming a network comprising a second bus interconnecting means between said input-output controller of one of said systems and said first bus means of another of said systems; means for communicating between said systems by at least two separate busses; means for communicating with a plurality of input-output data devices by at least two separate busses; said plurality of systems comprising means in at least one element for performing self-repair of said network; and said input-output controller comprising a plurality of operating modes including a bus extended mode for communicating between said interconnected systems, and a dynamic input-output mode for communicating with said input-output data devices coupled to said controller.

Claim 61

In combination: a plurality of elements; said plurality of elements comprising a signal processor, a mass memory and an input-output controller; first bus means for interconnecting in common said plurality of elements to form a distributed signal processing system; a plurality of said distributed signal processing systems forming a network comprising a second bus interconnecting means between said input-output controller bus means of another of said systems; means for communicating between said systems by at least two separate busses; means for communicating with a plurality of input-output data devices by at least two separate busses; said plurality of systems comprising means in at least one element for performing self-repair of said network; said input-output controller comprising a plurality of operating modes including a bus extended mode for communicating between said interconnected systems, and a dynamic input-output mode for communication with said input-output data devices coupled to said controller; and means for managing said network comprising a distributed operating system.

Claim 62

In combination: a plurality of elements; said plurality of elements comprising a signal processor, a mass memory and an input-output controller; first bus means for interconnecting in common said plurality of elements to form a distributed signal processing system; a plurality of said distributed signal processing systems forming a network comprising a second bus interconnecting means between said input-output controller bus means of another of said systems; means for communicating between said systems by at least two separate busses; means for communicating with a plurality of input-output data devices by at least two separate busses; said plurality of systems comprising means in at least one element for performing self-repair of said network; said input-output controller comprising a plurality of operating modes including a bus extended mode for communicating between said interconnected systems, and a dynamic input-output mode for communication with said input-output data devices coupled to said controller; and means for managing said network comprising a distributed operating system.

Claim 63

The combination as recited in claim 50 wherein: said distributed operating system comprises means for executive control in at least one of said systems.

Claim 64

The combination as recited in claim 50 wherein: said self-repair means comprises an element address register in each of said elements for removing a faulty element from operating service and replacing said faulty element with a spare element by changing an address in said address register.