Patent US4419808A successfully refreshed from Google Patents.
US4419808A
Expired / Lapsed
US
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Method of producing redundant ROM cells
Assignee: Conexant Systems LLC
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Filing: 1982-09-23
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Granted: 1983-12-13
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Expires: 2002-09-23
Abstract
Abstract The present invention comprises a unique FET with resistor in its drain lead of undoped polysilicon which may be characterized by high resistance in the absence of the application of a biasing voltage across the FET and the resistor when the FET is conducting, which biasing voltage irreversibly changes the resistor to a high state of conductivity thereby selectively providing the two logic states. This device may comprise a redundant cell for a ROM memory and may be uniquely fabricated utilizing VLSI MOS processing steps to provide a new manufacturing process.
Inventors
- 👤 Matthias L. Tam
- 👤 Frank Z. Custode
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:19
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; G; G11; G11C; G11C17/00; G11C17/14; G11C17/16; H10B; H10B20/00; H10D62/80; H10D62/83; H10D64/00; H10D64/60; H10D64/62; H10D88/00
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
103 words
A method for producing an electrically programmable very large scale integrated circuit having at least one redundant read only memory cell comprising the steps of: forming a gate oxide; growing field oxide around active regions of a substrate including the region of gate oxide; forming the gate, source and drain conductors of doped polysilicon; forming source and drain regions on opposite sides of the gate; forming a layer of undoped polysilicon on the doped polysilicon drain; and, forming contacts to the gate, source and drain whereby the layer of undoped polysilicon on the drain comprises a resistor connected in series with the drain.
Claim 2
Independent Claim
103 words
A method for producing an electrically programmable very large scale integrated circuit having at least one redundant read only memory cell comprising the steps of: forming a gate oxide; growing field oxide around active regions of a substrate including the region of gate oxide; forming the gate, source and drain conductors of doped polysilicon; forming source and drain regions on opposite sides of the gate; forming a layer of undoped polysilicon on the doped polysilicon drain; and, forming contacts to the gate, source and drain whereby the layer of undoped polysilicon on the drain comprises a resistor connected in series with the drain.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-12-12 | 1987-06-13 | 1987-12-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-12-12 | 1991-06-13 | 1991-12-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-12-12 | 1995-06-13 | 1995-12-13 | $7700.00 | Window Closed / Lapsed |