Read-only memory device

Claim 2

A read-only memory device, for storing binary data having first and second levels, respectively, comprising: first and second power supplies; a plurality of word lines; a plurality of bit lines intersecting said word lines and connected to said first power supply; a plurality of memory cells, each operatively connected to one of said word lines, one of said bit lines and said second power supply, some of said memory cells comprise metal insulator semiconductor transistors, each having a gate operatively connected to one of said word lines, a drain operatively connected to one of said bit lines and a source operatively connected to said second power supply, said binary data or the inversion of said binary data is written in said memory cells in dependence upon the number of first levels in said binary data belonging to each word line and the presence or absence of a metal insulator semiconductor transistor in each memory cell represents either the first level or the second level respectively; and a plurality of inversion storing means, each operatively connected to a one of said word lines, for storing and indicating that either said binary data or the inversion of said binary data is written in said memory cells belonging to each of said word lines.

Claim 3

A device as set forth in claim 1, further comprising a plurality of coincidence circuits, each connected to one of said bit lines and to said inversion storing means.

Claim 4

A read-only memory device as set forth in claim 1, wherein the presence of a metal insulator semiconductor transistor in each memory cell operatively connected to one word line corresponds to the first level when the number of the first levels in said binary data belonging to the one of said word lines is smaller than a first value; and the presence of a metal insulator semiconductor transistor in each memory cell operatively connected to the one word line corresponds to the second level when the number of the first levels in said binary data belonging to the one of said word lines is not smaller than said first value.

Claim 5

A read-only memory device as set forth in claim 1, further comprising an additional bit line intersecting said word lines and operatively connected to said first power supply, and wherein some of said plurality of inversion storing means comprise metal insulator semiconductor transistors, each having a gate operatively connected to one of said word lines, a drain operatively connected to said additional bit line and a source operatively connected to said second power supply, the presence or absence of a metal insulator semiconductor transistor at the intersection of each word line and said additional bit line being determined in dependence upon the number of first levels in said binary data belonging to each word line.

Claim 6

A read-only memory device as set forth in claim 1, further comprising an additional bit line intersecting said word lines and operatively connected to said first power supply, and wherein each of said inversion storing means comprises a metal insulator semiconductor transistor having a gate operatively connected to one of said word lines, a drain operatively connected to said additional bit line, a source operatively connected to said second power supply, a threshold voltage value and a channel region, the threshold voltage value of said metal insulator semiconductor transistor at the intersection of each word line and said additional bit line being determined by changing a concentration of impurity of the channel region of said metal insulator semiconductor transistor in dependence upon the number of first levels in said binary data belonging to each word line.

Claim 7

A read only memory device as set forth in claim 1, further comprising decoder means, operatively connected to said word lines, for selecting a word line using a high potential, and wherein the gates of said metal insulator semiconductor transistors have parasitic capacitances which require charging up by the high potential during the selection operation.

Claim 8

A read-only memory device comprising: first bit lines; a second bit line; a word line having associated therewith binary data having first and second bits; memory cells, each operatively connected between said word line and one of said first bit lines, for storing binary data or the inversion of the binary data in dependence upon the number of first bits in the binary data associated with said word line and being driven by said word line; inversion indicating means, operatively connected between said word line and said second bit line, for indicating that the binary data associated with said word line is stored as the binary data or as the inversion of the binary data; and a coincidence circuit, operatively connected to said first bit lines and said second bit line, wherein the binary data is stored as the inversion of the binary data said coincidence circuit converts the inversion of the binary data into the binary data.

Claim 9

A read-only memory device comprising: first bit lines; a second bit line; a word line having associated therewith binary data having first and second bits; memory cells, each operatively connected between said word line and one of said first bit lines, for storing binary data or the inversion of the binary data in dependence upon the number of first bits in the binary data associated with said word line and being driven by said word line; inversion indicating means, operatively connected between said word line and said second bit line, for indicating that the binary data associated with said word line is stored as the binary data or as the inversion of the binary data; and a coincidence circuit, operatively connected to said first bit lines and said second bit line, wherein the binary data is stored as the inversion of the binary data said coincidence circuit converts the inversion of the binary data into the binary data.

Claim 10

A read-only memory device as set forth in claim 7, wherein some of said memory cells comprise a transistor, the existence of said transistor being in dependence upon the number of first bits in the binary data and each existing said transistor having a gate operatively connected to said word line and being connected to one of said first bit lines.

Claim 11

A read only memory device as set forth in claim 8, further comprising decoder means, operatively connected to said word lines, for selecting a word line using a high potential, and wherein the gates of said transistors have parasitic capacitances which require charging up by the high potential during the selection operation.

Claim 12

A read-only memory device as set forth in claim 7, wherein said inversion indication means comprises a transistor, the existence of said transistor being in dependence upon the number of first bit in the binary data associated with said word line and each existing said transistor operatively connected between said word line and said second bit line.

Claim 13

A read-only memory device as set forth in claim 7, wherein said inversion indication means comprises a transistor, operatively connected between said word line and said second bit line, having a threshold which allows transistor operation in dependence upon the number of first bits in the binary data associated with said word line.

Claim 14

A read-only memory device, for storing binary data having first and second levels, respectively, comprising: first and second power supplies; a plurality of word lines; a plurality of bit lines intersecting said word lines and connected to said first power supply; a plurality of memory cells, each operatively connected to one of said word lines, one of said bit lines and said second power supply, some of said memory cells comprise metal insulator semicoductor transistors, each having a gate operatively connected to one of said word lines, a drain operatively connected to one of said bit lines and a source operatively connected to said second power supply, said binary data or the inversion of said binary data is written in said memory cells in dependence upon the number of first levels in said binary data belonging to each word line and the presence or absence of a metal insulator semiconductor transistor in each memory cell represents either the first level or the second level respectively; an additional bit line intersecting said word lines and operatively connected to said first power supply; and a plurality of inversion storing means, each operatively connected to a one of said word lines, for storing and indicating that either said binary data or the inversion of said binary data is written in said memory cells belonging to each of said word lines, some of said plurality of inversion storing means comprising metal insulator semiconductor transistors, each having a gate operatively connected to one of said word lines, a drain operatively connected to said additional bit line and a source operatively connected to said second power supply, the presence or absence of a metal insulator semiconductor transistor at the intersection of each word line and said additional bit line being determined in dependence upon the number of first levels in said binary data belonging to each word line.

Claim 15

A read-only memory device, for storing binary data having first and second levels, respectively, comprising: first and second power supplies; a plurality of word lines; a plurality of bit lines intersecting said word lines and connected to said first power supply; a plurality of memory cells, each operatively connected to one of said word lines, one of said bit lines and said second power supply, some of said memory cells comprise metal insulator semicoductor transistors, each having a gate operatively connected to one of said word lines, a drain operatively connected to one of said bit lines and a source operatively connected to said second power supply, said binary data or the inversion of said binary data is written in said memory cells in dependence upon the number of first levels in said binary data belonging to each word line and the presence or absence of a metal insulator semiconductor transistor in each memory cell represents either the first level or the second level respectively; an additional bit line intersecting said word lines and operatively connected to said first power supply; and a plurality of inversion storing means, each operatively connected to a one of said word lines, for storing and indicating that either said binary data or the inversion of said binary data is written in said memory cells belonging to each of said word lines, some of said plurality of inversion storing means comprising metal insulator semiconductor transistors, each having a gate operatively connected to one of said word lines, a drain operatively connected to said additional bit line and a source operatively connected to said second power supply, the presence or absence of a metal insulator semiconductor transistor at the intersection of each word line and said additional bit line being determined in dependence upon the number of first levels in said binary data belonging to each word line.

Claim 16

A read-only memory device, for storing binary data having first and second levels, respectively, comprising: first and second power supplies; a plurality of word lines; a plurality of bit lines intersecting said word lines and connected to said first power supply; a plurality of memory cells, each operatively connected to one of said word lines, one of said bit lines and said second power supply, some of said memory cells comprise metal insulator semiconductor transistors, each having a gate operatively connected to one of said word lines, a drain operatively connected to one of said bit lines and a source operatively connected to said second power supply, said binary data or the inversion of said binary data is written in said memory cells in dependence upon the number of first levels in said binary data belonging to each word line and the presence or absence of a metal insulator semiconductor transistor in each memory cell represents either the first level or the second level respectively; an additional bit line intersecting said word lines and operatively connected to said first power supply; and a plurality of inversion storing means, each operatively connected to one of said word lines, for storing and indicating that either said binary data or the inversin of said binary data is written in said memory cells belonging to each of said word lines, each of said inversion storing means comprising a metal insulator semiconductor transistor having a gate operatively connected to one of said word lines, a drain operatively connected to said additional bit line, a source operatively connected to said second power supply, a threshold voltage value and a channel region, the threshold voltage value of said metal insulator semiconductor transistor at the intersection of each word line and said additional bit line being determined by changing a concentration of impurity of the channel region of said metal insulator semiconductor transistor in dependence upon the number of first levels in said binary data belonging to each word line.

Claim 17

A read-only memory device, for storing binary data having first and second levels, respectively, comprising: first and second power supplies; a plurality of word lines; a plurality of bit lines intersecting said word lines and connected to said first power supply; a plurality of memory cells, each operatively connected to one of said word lines, one of said bit lines and said second power supply, some of said memory cells comprise metal insulator semiconductor transistors, each having a gate operatively connected to one of said word lines, a drain operatively connected to one of said bit lines and a source operatively connected to said second power supply, said binary data or the inversion of said binary data is written in said memory cells in dependence upon the number of first levels in said binary data belonging to each word line and the presence or absence of a metal insulator semiconductor transistor in each memory cell represents either the first level or the second level respectively; an additional bit line intersecting said word lines and operatively connected to said first power supply; and a plurality of inversion storing means, each operatively connected to one of said word lines, for storing and indicating that either said binary data or the inversin of said binary data is written in said memory cells belonging to each of said word lines, each of said inversion storing means comprising a metal insulator semiconductor transistor having a gate operatively connected to one of said word lines, a drain operatively connected to said additional bit line, a source operatively connected to said second power supply, a threshold voltage value and a channel region, the threshold voltage value of said metal insulator semiconductor transistor at the intersection of each word line and said additional bit line being determined by changing a concentration of impurity of the channel region of said metal insulator semiconductor transistor in dependence upon the number of first levels in said binary data belonging to each word line.

Claim 18

A read-only memory device comprising: first bit lines; a second bit line; a word line having associated therewith binary data having first and second bits; memory cells, each operatively connected between said word line and one of said first bit lines, for storing binary data or the inversion of the binary data in dependence upon the number of first bits in the binary data associated with said word line and being driven by said word line; inversion indication means, operatively connected between said word line and said second bit line, for indicating that the binary data associated with said word line is stored as the binary data or as the inversion of the binary data, said inversion indication means comprising a transistor, the existence of said transistor being in dependence upon the number of first bits in the binary data associated with said word line and each existing said transistor operatively connected between said word line and said second bit line; and a coincidence circuit, operatively connected to said first bit lines and said second bit line, wherein when the binary data is stored as the invergion of the binary data said coincidence circuit converts the inversion of the binary data into the binary data.

Claim 19

A read-only memory device comprising: first bit lines; a second bit line; a word line having associated therewith binary data having first and second bits; memory cells, each operatively connected between said word line and one of said first bit lines, for storing binary data or the inversion of the binary data in dependence upon the number of first bits in the binary data associated with said word line and being driven by said word line; inversion indication means, operatively connected between said word line and said second bit line, for indicating that the binary data associated with said word line is stored as the binary data or as the inversion of the binary data, said inversion indication means comprising a transistor, the existence of said transistor being in dependence upon the number of first bits in the binary data associated with said word line and each existing said transistor operatively connected between said word line and said second bit line; and a coincidence circuit, operatively connected to said first bit lines and said second bit line, wherein when the binary data is stored as the invergion of the binary data said coincidence circuit converts the inversion of the binary data into the binary data.

Claim 20

A read-only memory device comprising: first bit lines; a second bit line; a word line having associated therewith binary data having first and second bits; memory cells, each operatively connected between said word line and one of said first bit lines, for storing binary data or the inversion of the binary data in dependence upon the number of first bits in the binary data associated with said word line and being driven by said word line; inversion indication means, operatively connected between said word line and said second bit line, for indicating that the binary data associated with said word line is stored as the binary data or as the inversion of the binary data, said inversion indication means comprising a transistor, operatively connected between said word line and said second bit line, having a threshold which allows transistor operation in dependence upon the number of first bits in the binary data associated with said word line; and a coincidence circuit, operatively connected to said first bit lines and said second bit line, wherein when the binary data is stored as the inversion of the binary data said coincidence circuit converts the inversion of the binary data into the binary data.

Claim 21

A read-only memory device comprising: first bit lines; a second bit line; a word line having associated therewith binary data having first and second bits; memory cells, each operatively connected between said word line and one of said first bit lines, for storing binary data or the inversion of the binary data in dependence upon the number of first bits in the binary data associated with said word line and being driven by said word line; inversion indication means, operatively connected between said word line and said second bit line, for indicating that the binary data associated with said word line is stored as the binary data or as the inversion of the binary data, said inversion indication means comprising a transistor, operatively connected between said word line and said second bit line, having a threshold which allows transistor operation in dependence upon the number of first bits in the binary data associated with said word line; and a coincidence circuit, operatively connected to said first bit lines and said second bit line, wherein when the binary data is stored as the inversion of the binary data said coincidence circuit converts the inversion of the binary data into the binary data.