Integrated circuit compensatory regulator apparatus

Claim 2

Voltage control apparatus comprising: a semiconductor chip containing a plurality of bipolar transistor transistor logic circuits arranged to form a gate array, each of said bipolar transistor transistor logic circuits connected to be powered by a low power supply voltage and propagate input signals within a predetermined time period; voltage regulator circuit means for adjusting the value of an input voltage, said circuit means having an input terminal, an adjustment terminal, and an output terminal, said input terminal being connected to receive said input voltage and said output terminal being connected to apply said low power supply voltage to each of said bipolar transistor logic circuits; first resistive means being connected between said output and adjustment terminals of said regulator circuit means; and, second resistive means being included on said chip, one end of said second resistive element being connected to a common reference potential of said chip and the other end of said second resistive means being connected to said adjustment terminal, said voltage regulator circuit means being operative in response to changes in the resistance of said second resistive means to adjust said supply voltage so as to maintain said predetermined time period at a constant value.

Claim 3

The apparatus of claim 1 wherein said first resistive means has a resistance value R1 and said second resistive means has a resistance value R2, said voltage regulator circuit means adjusting said low power supply voltage in accordance with the following expression: +V=Vref (1+R2/R1) wherein +V corresponds to said low power supply voltage and Vref corresponds to the voltage between said output and adjustment terminals of said voltage regulator circuit means.

Claim 4

The apparatus of claim 2 wherein each of said bipolar logic circuits corresponds to a gate circuit including a multiemitter transistor having a base resistor connected to said low power supply voltage and said first and second resistive means having a predetermined ratio which is given by the following expression: R2/R1=(+V-VB)/Vref wherein VB corresponds to the value of base voltage of said multiemitter transistor.

Claim 5

The apparatus of claim 3 wherein said predetermined ratio equals 0.68.

Claim 6

The apparatus of claim 3 wherein each of said gate circuits is a high speed low power Schottky TTL gate.

Claim 7

The apparatus of claim 1 wherein said voltage regulator circuit means is included as an integral part of said semiconductor chip.

Claim 8

The apparatus of claim 1 wherein said first resistive means is selected to have a fixed minimum tolerance so as to enable said voltage regulator circuit means to respond to slight changes in said resistance of said second resistive means.

Claim 9

The apparatus of claim 1 wherein each of said bipolar logic circuits corresponds to a gate circuit which includes a multiemitter transistor having a base resistor connected directly to said low power supply voltage and wherein said changes in resistances of said second resistive means represents corresponding changes in the current flowing through said base resistor.

Claim 10

The apparatus of claim 8 wherein said second resistive means consists of a plurality of parallel resistors located on said chip which are identical in construction to said base resistor for accurately reflecting changes in said multiemitter transistor circuit tolerances using said second resistive means.

Claim 11

The apparatus of claim 9 wherein said plurality of parallel resistors are distributed throughout said chip.

Claim 12

Voltage control apparatus comprising: a number of semiconductor chips, each containing a plurality of bipolar transistor transistor logic circuits arranged to form a gate array, each of said bipolar transistor logic circuits connected to be powered by low power supply voltage and provide a predetermined propagation delay for signals applied thereto; a plurality of voltage regulator circuits corresponding in number to said number of semiconductor chips, each of said plurality of regulator circuits having an input terminal, an output terminal and an adjustment terminal, said input terminal of each regulator circuit being connected to receive an input voltage and said output terminal of each regulator circuit being connected to apply said low power supply voltage to a different one of said number of semiconductor chips; a plurality of first resistors, each of said first resistors being connected between said output and adjustment terminals of a different one of said plurality of regulator circuits; and, a plurality of second resistors, each of said second resistors being included on a different one of said chips, one end of each second resistor being connected to a common reference potential of said chip and the other end of each said second resistor being connected to the regulator circuit connected to power said chip, each of said voltage regulator circuits being operative in response to any changes in the resistance of said second resistor associated therewith to adjust said low power supply voltage for maintaining a uniform propagation delay of signals through said bipolar logic circuits.

Claim 13

Voltage control apparatus comprising: a number of semiconductor chips, each containing a plurality of bipolar transistor transistor logic circuits arranged to form a gate array, each of said bipolar transistor logic circuits connected to be powered by low power supply voltage and provide a predetermined propagation delay for signals applied thereto; a plurality of voltage regulator circuits corresponding in number to said number of semiconductor chips, each of said plurality of regulator circuits having an input terminal, an output terminal and an adjustment terminal, said input terminal of each regulator circuit being connected to receive an input voltage and said output terminal of each regulator circuit being connected to apply said low power supply voltage to a different one of said number of semiconductor chips; a plurality of first resistors, each of said first resistors being connected between said output and adjustment terminals of a different one of said plurality of regulator circuits; and, a plurality of second resistors, each of said second resistors being included on a different one of said chips, one end of each second resistor being connected to a common reference potential of said chip and the other end of each said second resistor being connected to the regulator circuit connected to power said chip, each of said voltage regulator circuits being operative in response to any changes in the resistance of said second resistor associated therewith to adjust said low power supply voltage for maintaining a uniform propagation delay of signals through said bipolar logic circuits.

Claim 14

The apparatus of claim 11 wherein said input voltage applied to all of said plurality of voltage regulator circuits is unregulated.

Claim 15

The apparatus of claim 11 wherein each of said first resistors has a resistance value R1 and each of said second resistors has a resistance value R2, each of said voltage regulator circuits adjusting said low power supply voltage in accordance with the following expression: +V=Vref (1=R2/R1) wherein +V corresponds to said low power supply voltage and Vref corresponds to the voltage between said output and adjustment terminals of said each voltage regulator circuit.

Claim 16

The apparatus of claim 3 wherein each of said bipolar logic circuits of each chip corresponds to a gate circuit including a multiemitter transistor having a base resistor connected to said low power supply voltage and said first and second resistors having a predetermined ratio which is given by the following expression: R1/R2=(+V-VB)/Vref wherein VB corresponds to the value of base voltage of said multiemitter transistor.

Claim 17

The apparatus of claim 14 wherein said predetermined ratio equals 0.68.

Claim 18

The apparatus of claim 11 wherein each said voltage regulator circuit is included as an integral part of said semiconductor chip powered by said voltage regulator circuit.

Claim 19

The apparatus of claim 11 wherein each of said first resistors is selected to have a fixed minimum tolerance so as to enable said voltage regulator circuit connected therewith to respond to slight changes in said resistance of said second resistor connected therewith.

Claim 20

The apparatus of claim 11 wherein each of said bipolar logic circuits of each chip corresponds to a gate circuit which includes a multiemitter transistor having a base resistor connected directly to said low power supply voltage and wherein said changes in resistances of said second resistor located on said chip represents corresponding changes in the current flowing through said base resistor.

Claim 21

The apparatus of claim 18 wherein each of said second resistors consists of a plurality of parallel resistors located on said chip which are identical in construction to said base resistor for accurately reflecting changes in said multiemitter transistor circuit tolerances in said second resistor.

Claim 22

The apparatus of claim 11 wherein each of said plurality of voltage regulator circuits are mounted on a common substrate.

Claim 23

The apparatus of claim 11 wherein each of said plurality of voltage regulator circuits and said semiconductor chip are mounted on a common substrate.

Claim 24

Voltage control apparatus comprising: a semiconductor chip including: a plurality of bipolar transistor transistor logic circuits connected as a gate array, each of said bipolar logic circuits connected to be powered by a low power supply voltage and connected to receive input signals upon which a predetermined logical operation will be performed and the result provided after a predetermined propagation delay; and a first resistive element having one end connected to a common reference potential of said chip; a second resistive element located off said chip, conductor means for connecting one end of said second resistive element to the other end of said first resistive element forming a common junction; and, a voltage regulator circuit having an input terminal, an adjustment terminal and an output terminal, said input terminal being connected to receive an input voltage, said adjustment terminal being connected to said common junction and said output terminal being connected to apply said low power supply voltage to each of said bipolar transistor logic circuits, said voltage regulator circuit being operative to adjust said low power supply voltage in accordance with changes in the resistance of said first resistive element so as to maintain said predetermined propagation delay through said array uniform.

Claim 25

Voltage control apparatus comprising: a semiconductor chip including: a plurality of bipolar transistor transistor logic circuits connected as a gate array, each of said bipolar logic circuits connected to be powered by a low power supply voltage and connected to receive input signals upon which a predetermined logical operation will be performed and the result provided after a predetermined propagation delay; and a first resistive element having one end connected to a common reference potential of said chip; a second resistive element located off said chip, conductor means for connecting one end of said second resistive element to the other end of said first resistive element forming a common junction; and, a voltage regulator circuit having an input terminal, an adjustment terminal and an output terminal, said input terminal being connected to receive an input voltage, said adjustment terminal being connected to said common junction and said output terminal being connected to apply said low power supply voltage to each of said bipolar transistor logic circuits, said voltage regulator circuit being operative to adjust said low power supply voltage in accordance with changes in the resistance of said first resistive element so as to maintain said predetermined propagation delay through said array uniform.

Claim 26

The apparatus of claim 22 wherein said second resistive element has a resistance value R1 and said first resistive element has a resistance value R2, said voltage regulator circuit adjusting said low power supply voltage in accordance with the following expression: +V=Vref (1+R2/R1) wherein +V corresponds to said low power supply voltage and Vref corresponds to the voltage between said output and adjustment terminals of said voltage regulator circuit.

Claim 27

The apparatus of claim 23 wherein each of said bipolar logic circuits corresponds to a gate circuit including a multiemitter transistor having a base resistor connected to said low power supply voltage and said first and second resistive elements having a predetermined ratio which is given by the following expression: R2/R1=(+V-VB)/Vref wherein VB corresponds to the value of base voltage of said multiemitter transistor.

Claim 28

The apparatus of claim 24 wherein said predetermined ratio equals 0.68.

Claim 29

The apparatus of claim 24 wherein said voltage regulator circuit is included as an integral part of said semiconductor chip.

Claim 30

The apparatus of claim 24 wherein said second resistive element is selected to have a fixed minimum tolerance so as to enable said voltage regulator circuit to respond to slight changes in said resistance of said first resistive element.

Claim 31

The apparatus of claim 22 wherein each of said bipolar logic circuits corresponds to a gate circuit which includes a multiemitter transistor having a base resistor connected directly to said low power supply voltage and wherein said changes in resistances of said first resistive element represents corresponding changes in the current flowing through said base resistor.

Claim 32

The apparatus of claim 28 wherein said first resistive element consists of a plurality of parallel resistors located on said chip which are identical in construction to said base resistor for accurately reflecting changes in said multiemitter transistor circuit tolerances using said first resistive element.

Claim 33

The apparatus of claim 29 wherein said plurality of parallel resistors are distributed throughout said chip.