Patent US4447745A successfully refreshed from Google Patents.
US4447745A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Buffer circuit including a current leak circuit for maintaining the charged voltages
Assignee: Fujitsu Ltd
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Filing: 1981-11-18
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Granted: 1984-05-08
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Expires: 2001-11-18
Abstract
Abstract A semiconductor circuit used as a buffer circuit having an input stage circuit for receiving an input clock signal and an inverted input clock signal, a bootstrap circuit including a transistor for receiving the output of the input stage circuit and for maintaining the gate voltage of the transistor at a high level during the standby period, and an output circuit, including a transistor which is switched on and off by the output of the bootstrap circuit, for generating an output clock signal; the semiconductor circuit further comprising a current leak circuit for maintaining, during the standby period, the voltage of a point in the semiconductor circuit which is charged during the standby period at the value corresponding to the voltage of the power source, whereby the delay of the output clock signal, caused of the fluctuation by the voltage of the power supply during the standby period, is improved and then the high speed access time in the dynamic memory is carried out.
Inventors
- 👤 Yoshihiro Takemae
- 👤 Seiji Enomoto
- 👤 Shigeki Nozaki
- 👤 Tsutomu Mezawa
- 👤 Katsuhiko Kabashima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:04
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C11/41; G11C11/413; G11C11/417; G11C11/418; H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01728; H03K19/01735; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/01855
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
252 words
A semiconductor circuit, having first and second power terminals respectively connectable to receive a power source voltage and a reference voltage, and used as a buffer circuit for providing an output clock signal in response to an input clock signal and an inverted input clock signal, comprising: an input stage circuit, operatively connected to receive the input clock signal and the inverted input clock signal, for generating an output signal at a node in response thereto, the node being charged and maintained at the power source voltage during a standby period in which the input clock signal has a voltage lower than the voltage of the inverted input clock signal; a bootstrap circuit, operatively connected to said input stage circuit, for generating a boosted signal in response to the output signal of said input stage circuit, said bootstrap circuit including a first field effect transistor operatively connected to the node, for receiving the output signal of said input stage circuit; an output circuit, operatively connected to said bootstrap circuit, for generating the output clock signal, said output circuit including a second field effect transistor operatively connected to said bootstrap circuit for receiving the boosted signal; and a current leak circuit operatively connected between the node of said input stage circuit and said second power terminal, for maintaining the voltage of the node being charged during the standby period at a value corresponding to the power source voltage, by leaking excess charges at the node to lower the voltage level of the node.
Claim 2
Dependent Claim
252 words
A semiconductor circuit, having first and second power terminals respectively connectable to receive a power source voltage and a reference voltage, and used as a buffer circuit for providing an output clock signal in response to an input clock signal and an inverted input clock signal, comprising: an input stage circuit, operatively connected to receive the input clock signal and the inverted input clock signal, for generating an output signal at a node in response thereto, the node being charged and maintained at the power source voltage during a standby period in which the input clock signal has a voltage lower than the voltage of the inverted input clock signal; a bootstrap circuit, operatively connected to said input stage circuit, for generating a boosted signal in response to the output signal of said input stage circuit, said bootstrap circuit including a first field effect transistor operatively connected to the node, for receiving the output signal of said input stage circuit; an output circuit, operatively connected to said bootstrap circuit, for generating the output clock signal, said output circuit including a second field effect transistor operatively connected to said bootstrap circuit for receiving the boosted signal; and a current leak circuit operatively connected between the node of said input stage circuit and said second power terminal, for maintaining the voltage of the node being charged during the standby period at a value corresponding to the power source voltage, by leaking excess charges at the node to lower the voltage level of the node.
Claim 3
Dependent Claim
219 words
A semiconductor circuit, having first and second power terminals respectively connectable to receive a power source voltage and a reference voltage, and used as a buffer circuit for providing an output clock signal in response to an input clock signal and an inverted input clock signal, comprising: an input stage delay circuit, operatively connected to receive the input clock signal and the inverted input clock signal, for generating an output signal at a node in response thereto, the node being charged and maintained at the power source voltage during a standby period in which the input clock signal has a voltage lower than the voltage of the inverted input clock signal; a bootstrap circuit, operatively connected to said input stage delay circuit, for responding to the voltage of the node after the standby period by outputting a boosted signal; an output circuit, operatively connected to said bootstrap circuit, for receiving the boosted signal of said bootstrap circuit and for generating the output clock signal; and a current leak circuit, operatively connected between said input stage delay circuit and said second power terminal, for maintaining the voltage of the node being charged during the standby period at a value corresponding to the power source voltage by leaking excess charges at the node to lower the voltage level of the node.
Claim 4
Dependent Claim
219 words
A semiconductor circuit, having first and second power terminals respectively connectable to receive a power source voltage and a reference voltage, and used as a buffer circuit for providing an output clock signal in response to an input clock signal and an inverted input clock signal, comprising: an input stage delay circuit, operatively connected to receive the input clock signal and the inverted input clock signal, for generating an output signal at a node in response thereto, the node being charged and maintained at the power source voltage during a standby period in which the input clock signal has a voltage lower than the voltage of the inverted input clock signal; a bootstrap circuit, operatively connected to said input stage delay circuit, for responding to the voltage of the node after the standby period by outputting a boosted signal; an output circuit, operatively connected to said bootstrap circuit, for receiving the boosted signal of said bootstrap circuit and for generating the output clock signal; and a current leak circuit, operatively connected between said input stage delay circuit and said second power terminal, for maintaining the voltage of the node being charged during the standby period at a value corresponding to the power source voltage by leaking excess charges at the node to lower the voltage level of the node.
Claim 5
Dependent Claim
249 words
A semiconductor circuit, having first and second power terminals respectively connectable to receive a power source voltage and a reference voltage, and used as a buffer circuit for providing an output clock signal in response to an input clock signal and an inverted input clock signal, comprising: an input stage circuit including an input delay circuit, operatively connected to receive the input clock signal and the inverted input clock signal, for generating an output signal at a node, the node being charged and maintained at the power source voltage during the standby period in which the input clock signal has a voltage level lower than the voltage level of the inverted input clock signal; a bootstrap circuit, operatively connected to said input delay circuit, for responding to the voltage of the node by generating a boosted signal in response to the output signal of said input delay circuit, said bootstrap circuit including at least a first stage transistor and a second stage transistor operatively connected to said first stage transistor at a second node; an output circuit, operativley connected to said bootstrap circuit, for receiving the boosted signal and for generating the output clock signal; and a current leak circuit, operatively connected between said second node and said second power terminal, for maintaining the voltage of said second node being charged during the standby period at a value corresponding to the power source voltage, by leaking excess charges at the node to lower the voltage level of the node.
Claim 6
Dependent Claim
249 words
A semiconductor circuit, having first and second power terminals respectively connectable to receive a power source voltage and a reference voltage, and used as a buffer circuit for providing an output clock signal in response to an input clock signal and an inverted input clock signal, comprising: an input stage circuit including an input delay circuit, operatively connected to receive the input clock signal and the inverted input clock signal, for generating an output signal at a node, the node being charged and maintained at the power source voltage during the standby period in which the input clock signal has a voltage level lower than the voltage level of the inverted input clock signal; a bootstrap circuit, operatively connected to said input delay circuit, for responding to the voltage of the node by generating a boosted signal in response to the output signal of said input delay circuit, said bootstrap circuit including at least a first stage transistor and a second stage transistor operatively connected to said first stage transistor at a second node; an output circuit, operativley connected to said bootstrap circuit, for receiving the boosted signal and for generating the output clock signal; and a current leak circuit, operatively connected between said second node and said second power terminal, for maintaining the voltage of said second node being charged during the standby period at a value corresponding to the power source voltage, by leaking excess charges at the node to lower the voltage level of the node.
Claim 7
Dependent Claim
307 words
A semiconductor circuit, having first and second power terminals respectively connectable to receive a power source voltage and a reference voltage, and used as a buffer circuit for providing an output clock signal in response to an input clock signal and an inverted input clock signal, comprising: an input stage circuit including an input delay circuit, operatively connected to receive the input clock signal and the inverted input clock signal, for generating an output signal at a first node in response thereto, the first node being charged and maintained at the power source voltage during a standby period in which the input clock signal has a voltage level lower than a voltage level of the inverted input clock signal; a bootstrap circuit, operatively connected to said input delay circuit, for generating a boosted signal in response to the output signal of said input delay circuit, said bootstrap circuit including a first stage having at least a first transistor and a second transistor operatively connected to said first transistor at a second node, and a second stage having a third transistor operatively connected to said first and second transistors at the second node; an output circuit, operatively connected to said bootstrap circuit, for receiving the boosted signal and for generating the output clock signal; and first and second current leak circuits, said first current leak circuit operatively connected to the second node between said first and second transistors in said first stage and said second power terminal, said second current leak circuit operatively connected between the first node of said input delay circuit and said second power terminal, the voltages of the first and second nodes being maintained at a value corresponding to the power source voltage by leaking excess charges at the first and second nodes to lower the voltage level of the first and second nodes.
Claim 8
Dependent Claim
307 words
A semiconductor circuit, having first and second power terminals respectively connectable to receive a power source voltage and a reference voltage, and used as a buffer circuit for providing an output clock signal in response to an input clock signal and an inverted input clock signal, comprising: an input stage circuit including an input delay circuit, operatively connected to receive the input clock signal and the inverted input clock signal, for generating an output signal at a first node in response thereto, the first node being charged and maintained at the power source voltage during a standby period in which the input clock signal has a voltage level lower than a voltage level of the inverted input clock signal; a bootstrap circuit, operatively connected to said input delay circuit, for generating a boosted signal in response to the output signal of said input delay circuit, said bootstrap circuit including a first stage having at least a first transistor and a second transistor operatively connected to said first transistor at a second node, and a second stage having a third transistor operatively connected to said first and second transistors at the second node; an output circuit, operatively connected to said bootstrap circuit, for receiving the boosted signal and for generating the output clock signal; and first and second current leak circuits, said first current leak circuit operatively connected to the second node between said first and second transistors in said first stage and said second power terminal, said second current leak circuit operatively connected between the first node of said input delay circuit and said second power terminal, the voltages of the first and second nodes being maintained at a value corresponding to the power source voltage by leaking excess charges at the first and second nodes to lower the voltage level of the first and second nodes.
Claim 9
Dependent Claim
30 words
A semiconductor circuit used as a buffer circuit as defined in claim 1, 2, 3 or 4, wherein said current leak circuit comprises field effect transistors operatively connected in series.
Claim 10
Dependent Claim
39 words
A semiconductor circuit used as a buffer circuit as defined in claim 1, 2, 3 or 4, wherein said current leak circuit comprises a field effect transistor, and a resistor operatively connected in series with said field effect transistor.
Claim 11
Dependent Claim
27 words
A semiconductor circuit used as a buffer circuit as defined in claim 1, 2, 3 or 4, wherein said current leak circuit comprises a field effect transistor.
Claim 12
Dependent Claim
25 words
A semiconductor circuit used as a buffer circuit as defined in claim 1, 2, 3 or 4, wherein said current leak circuit comprises a resistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-05-08 | 1987-11-07 | 1988-05-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-05-08 | 1991-11-07 | 1992-05-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-05-08 | 1995-11-07 | 1996-05-08 | $7700.00 | Window Closed / Lapsed |